mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-10 20:54:24 +00:00
spi: add eeprom example
This commit is contained in:
Michael (XIAO Xufeng)
@@ -0,0 +1,4 @@
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idf_component_register(SRCS "spi_eeprom.c"
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LDFRAGMENTS "linker.lf"
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INCLUDE_DIRS ".")
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@@ -0,0 +1,6 @@
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#
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# Main Makefile. This is basically the same as a component makefile.
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#
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# (Uses default behaviour of compiling all source files in directory, adding 'include' to include path.)
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COMPONENT_ADD_LDFRAGMENTS += "linker.lf"
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@@ -0,0 +1,24 @@
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# This example supports running on the SPI1 bus, which is shared with SPI flash accessed by the
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# cache. When doing transaction on SPI1 bus, data cannot be fetched from the flash, so all the data
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# used during this time should be put into the internal RAM.
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[mapping:eeprom]
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archive: libeeprom.a
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entries:
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* (noflash)
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[mapping:ext_driver]
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archive: libdriver.a
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entries:
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# gpio_set_level, gpio_get_level, gpio_context, _gpio_hal, etc...
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gpio (noflash)
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[mapping:ext_soc]
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archive: libsoc.a
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entries:
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gpio_hal (noflash)
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[mapping:ext_newlib]
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archive: libnewlib.a
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entries:
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time:usleep (noflash)
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@@ -0,0 +1,324 @@
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/*
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This code demonstrates how to use the SPI master half duplex mode to read/write a AT932C46D
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EEPROM (8-bit mode).
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This example code is in the Public Domain (or CC0 licensed, at your option.)
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Unless required by applicable law or agreed to in writing, this
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software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, either express or implied.
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*/
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#include "spi_eeprom.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "driver/gpio.h"
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#include <unistd.h>
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#include "esp_log.h"
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#include <sys/param.h>
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#include "sdkconfig.h"
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#define EEPROM_BUSY_TIMEOUT_MS 5
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#define EEPROM_CLK_FREQ (1*1000*1000) //When powered by 3.3V, EEPROM max freq is 1MHz
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#define EEPROM_INPUT_DELAY_NS ((1000*1000*1000/EEPROM_CLK_FREQ)/2+20)
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#define ADDR_MASK 0x7f
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#define CMD_EWDS 0x200
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#define CMD_WRAL 0x200
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#define CMD_ERAL 0x200
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#define CMD_EWEN 0x200
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#define CMD_CKBS 0x000
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#define CMD_READ 0x300
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#define CMD_ERASE 0x380
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#define CMD_WRITE 0x280
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#define ADD_EWDS 0x00
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#define ADD_WRAL 0x20
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#define ADD_ERAL 0x40
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#define ADD_EWEN 0x60
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/// Context (config and data) of the spi_eeprom
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struct eeprom_context_t{
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eeprom_config_t cfg; ///< Configuration by the caller.
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spi_device_handle_t spi; ///< SPI device handle
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xSemaphoreHandle ready_sem; ///< Semaphore for ready signal
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};
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typedef struct eeprom_context_t eeprom_context_t;
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static const char TAG[] = "eeprom";
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// Workaround: The driver depends on some data in the flash and cannot be placed to DRAM easily for
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// now. Using the version in LL instead.
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#define gpio_set_level gpio_set_level_patch
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#include "hal/gpio_ll.h"
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static inline esp_err_t gpio_set_level_patch(gpio_num_t gpio_num, uint32_t level)
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{
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gpio_ll_set_level(&GPIO, gpio_num, level);
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return ESP_OK;
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}
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static esp_err_t eeprom_simple_cmd(eeprom_context_t *ctx, uint16_t cmd)
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{
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spi_transaction_t t = {
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.cmd = cmd,
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.user = ctx
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};
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return spi_device_polling_transmit(ctx->spi, &t);
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}
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static esp_err_t eeprom_wait_done(eeprom_context_t* ctx)
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{
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//have to keep cs low for 250ns
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usleep(1);
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//clear signal
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if (ctx->cfg.intr_used) {
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xSemaphoreTake(ctx->ready_sem, 0);
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gpio_set_level(ctx->cfg.cs_io, 1);
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gpio_intr_enable(ctx->cfg.miso_io);
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//Max processing time is 5ms, tick=1 may happen very soon, set to 2 at least
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uint32_t tick_to_wait = MAX(EEPROM_BUSY_TIMEOUT_MS / portTICK_PERIOD_MS, 2);
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BaseType_t ret = xSemaphoreTake(ctx->ready_sem, tick_to_wait);
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gpio_intr_disable(ctx->cfg.miso_io);
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gpio_set_level(ctx->cfg.cs_io, 0);
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if (ret != pdTRUE) return ESP_ERR_TIMEOUT;
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} else {
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bool timeout = true;
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gpio_set_level(ctx->cfg.cs_io, 1);
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for (int i = 0; i < EEPROM_BUSY_TIMEOUT_MS * 1000; i ++) {
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if (gpio_get_level(ctx->cfg.miso_io)) {
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timeout = false;
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break;
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}
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usleep(1);
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}
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gpio_set_level(ctx->cfg.cs_io, 0);
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if (timeout) return ESP_ERR_TIMEOUT;
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}
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return ESP_OK;
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}
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static void cs_high(spi_transaction_t* t)
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{
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ESP_EARLY_LOGV(TAG, "cs high %d.", ((eeprom_context_t*)t->user)->cfg.cs_io);
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gpio_set_level(((eeprom_context_t*)t->user)->cfg.cs_io, 1);
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}
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static void cs_low(spi_transaction_t* t)
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{
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gpio_set_level(((eeprom_context_t*)t->user)->cfg.cs_io, 0);
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ESP_EARLY_LOGV(TAG, "cs low %d.", ((eeprom_context_t*)t->user)->cfg.cs_io);
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}
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void ready_rising_isr(void* arg)
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{
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eeprom_context_t* ctx = (eeprom_context_t*)arg;
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xSemaphoreGive(ctx->ready_sem);
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ESP_EARLY_LOGV(TAG, "ready detected.");
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}
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esp_err_t spi_eeprom_deinit(eeprom_context_t* ctx)
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{
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spi_bus_remove_device(ctx->spi);
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if (ctx->cfg.intr_used) {
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vSemaphoreDelete(ctx->ready_sem);
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}
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free(ctx);
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return ESP_OK;
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}
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esp_err_t spi_eeprom_init(const eeprom_config_t *cfg, eeprom_context_t** out_ctx)
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{
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esp_err_t err = ESP_OK;
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if (cfg->intr_used && cfg->host == SPI1_HOST) {
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ESP_LOGE(TAG, "interrupt cannot be used on SPI1 host.");
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return ESP_ERR_INVALID_ARG;
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}
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eeprom_context_t* ctx = (eeprom_context_t*)malloc(sizeof(eeprom_context_t));
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if (!ctx) return ESP_ERR_NO_MEM;
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*ctx = (eeprom_context_t) {
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.cfg = *cfg,
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};
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spi_device_interface_config_t devcfg={
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.command_bits = 10,
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.clock_speed_hz = EEPROM_CLK_FREQ,
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.mode = 0, //SPI mode 0
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/*
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* The timing requirements to read the busy signal from the EEPROM cannot be easily emulated
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* by SPI transactions. We need to control CS pin by SW to check the busy signal manually.
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*/
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.spics_io_num = -1,
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.queue_size = 1,
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.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_POSITIVE_CS,
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.pre_cb = cs_high,
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.post_cb = cs_low,
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.input_delay_ns = EEPROM_INPUT_DELAY_NS, //the EEPROM output the data half a SPI clock behind.
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};
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//Attach the EEPROM to the SPI bus
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err = spi_bus_add_device(ctx->cfg.host, &devcfg, &ctx->spi);
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if (err != ESP_OK) {
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goto cleanup;
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}
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gpio_set_level(ctx->cfg.cs_io, 0);
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gpio_config_t cs_cfg = {
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.pin_bit_mask = BIT64(ctx->cfg.cs_io),
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.mode = GPIO_MODE_OUTPUT,
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};
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gpio_config(&cs_cfg);
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if (ctx->cfg.intr_used) {
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ctx->ready_sem = xSemaphoreCreateBinary();
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if (ctx->ready_sem == NULL) {
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err = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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gpio_set_intr_type(ctx->cfg.miso_io, GPIO_INTR_POSEDGE);
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err = gpio_isr_handler_add(ctx->cfg.miso_io, ready_rising_isr, ctx);
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if (err != ESP_OK) {
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goto cleanup;
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}
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gpio_intr_disable(ctx->cfg.miso_io);
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}
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*out_ctx = ctx;
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return ESP_OK;
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cleanup:
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if (ctx->spi) {
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spi_bus_remove_device(ctx->spi);
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ctx->spi = NULL;
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}
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if (ctx->ready_sem) {
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vSemaphoreDelete(ctx->ready_sem);
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ctx->ready_sem = NULL;
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}
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free(ctx);
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return err;
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}
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esp_err_t spi_eeprom_read(eeprom_context_t* ctx, uint8_t addr, uint8_t* out_data)
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{
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spi_transaction_t t = {
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.cmd = CMD_READ | (addr & ADDR_MASK),
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.rxlength = 8,
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.flags = SPI_TRANS_USE_RXDATA,
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.user = ctx,
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};
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esp_err_t err = spi_device_polling_transmit(ctx->spi, &t);
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if (err!= ESP_OK) return err;
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*out_data = t.rx_data[0];
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return ESP_OK;
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}
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esp_err_t spi_eeprom_erase(eeprom_context_t* ctx, uint8_t addr)
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{
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esp_err_t err;
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err = spi_device_acquire_bus(ctx->spi, portMAX_DELAY);
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if (err != ESP_OK) return err;
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err = eeprom_simple_cmd(ctx, CMD_ERASE | (addr & ADDR_MASK));
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if (err == ESP_OK) {
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err = eeprom_wait_done(ctx);
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}
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spi_device_release_bus(ctx->spi);
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return err;
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}
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esp_err_t spi_eeprom_write(eeprom_context_t* ctx, uint8_t addr, uint8_t data)
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{
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esp_err_t err;
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err = spi_device_acquire_bus(ctx->spi, portMAX_DELAY);
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if (err != ESP_OK) return err;
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spi_transaction_t t = {
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.cmd = CMD_WRITE | (addr & ADDR_MASK),
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.length = 8,
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.flags = SPI_TRANS_USE_TXDATA,
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.tx_data = {data},
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.user = ctx,
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};
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err = spi_device_polling_transmit(ctx->spi, &t);
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if (err == ESP_OK) {
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err = eeprom_wait_done(ctx);
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}
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spi_device_release_bus(ctx->spi);
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return err;
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}
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esp_err_t spi_eeprom_write_enable(eeprom_context_t* ctx)
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{
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return eeprom_simple_cmd(ctx, CMD_EWEN | ADD_EWEN);
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}
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esp_err_t spi_eeprom_write_disable(eeprom_context_t* ctx)
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{
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return eeprom_simple_cmd(ctx, CMD_EWDS | ADD_EWDS);
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}
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esp_err_t spi_eeprom_erase_all(eeprom_context_t* ctx)
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{
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#if !CONFIG_EXAMPLE_5V_COMMANDS
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//not supported in 3.3V VCC
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ESP_LOGE(TAG, "erase all not supported by EEPROM under 3.3V VCC");
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return ESP_ERR_NOT_SUPPORTED;
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#endif
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esp_err_t err;
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err = spi_device_acquire_bus(ctx->spi, portMAX_DELAY);
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if (err != ESP_OK) return err;
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err = eeprom_simple_cmd(ctx, CMD_ERAL | ADD_ERAL);
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if (err == ESP_OK) {
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err = eeprom_wait_done(ctx);
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}
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spi_device_release_bus(ctx->spi);
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return err;
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}
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esp_err_t spi_eeprom_write_all(eeprom_context_t* ctx, uint8_t data)
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{
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#if !CONFIG_EXAMPLE_5V_COMMANDS
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//not supported in 3.3V VCC
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ESP_LOGE(TAG, "write all not supported by EEPROM under 3.3V VCC");
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return ESP_ERR_NOT_SUPPORTED;
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#endif
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esp_err_t err;
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err = spi_device_acquire_bus(ctx->spi, portMAX_DELAY);
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if (err != ESP_OK) return err;
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spi_transaction_t t = {
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.cmd = CMD_WRAL | ADD_WRAL,
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.length = 8,
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.flags = SPI_TRANS_USE_TXDATA,
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.tx_data = {data},
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.user = ctx,
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};
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err = spi_device_polling_transmit(ctx->spi, &t);
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if (err == ESP_OK) {
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err = eeprom_wait_done(ctx);
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}
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spi_device_release_bus(ctx->spi);
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return err;
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}
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@@ -0,0 +1,123 @@
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/*
|
||||
This code demonstrates how to use the SPI master half duplex mode to read/write a AT932C46D
|
||||
EEPROM (8-bit mode).
|
||||
|
||||
This example code is in the Public Domain (or CC0 licensed, at your option.)
|
||||
|
||||
Unless required by applicable law or agreed to in writing, this
|
||||
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
CONDITIONS OF ANY KIND, either express or implied.
|
||||
*/
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#pragma once
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#include "driver/spi_master.h"
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#include "driver/gpio.h"
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#include "sdkconfig.h"
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/// Configurations of the spi_eeprom
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typedef struct {
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spi_host_device_t host; ///< The SPI host used, set before calling `spi_eeprom_init()`
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gpio_num_t cs_io; ///< CS gpio number, set before calling `spi_eeprom_init()`
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gpio_num_t miso_io; ///< MISO gpio number, set before calling `spi_eeprom_init()`
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bool intr_used; ///< Whether to use polling or interrupt when waiting for write to be done. Set before calling `spi_eeprom_init()`.
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} eeprom_config_t;
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typedef struct eeprom_context_t* eeprom_handle_t;
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/**
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* @brief Initialize the hardware.
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*
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* @param config Configuration of the EEPROM
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* @param out_handle Output context of EEPROM communication.
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* @return
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* - ESP_OK: on success
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* - ESP_ERR_INVALID_ARG: If the configuration in the context is incorrect.
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* - ESP_ERR_NO_MEM: if semaphore create failed.
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* - or other return value from `spi_bus_add_device()` or `gpio_isr_handler_add()`.
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*/
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esp_err_t spi_eeprom_init(const eeprom_config_t *config, eeprom_handle_t* out_handle);
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/**
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* @brief Release the resources used by the EEPROM.
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*
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* @param handle Context of EEPROM communication.
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* @return Always ESP_OK
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*/
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esp_err_t spi_eeprom_deinit(eeprom_handle_t handle);
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/**
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* @brief Read a byte from the EEPROM.
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*
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* @param handle Context of EEPROM communication.
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* @param addr Address to read.
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* @param out_data Buffer to output the read data.
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* @return return value from `spi_device_polling_transmit()`.
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*/
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esp_err_t spi_eeprom_read(eeprom_handle_t handle, uint8_t addr, uint8_t* out_data);
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/**
|
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* @brief Erase a byte in the EEPROM.
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*
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* @param handle Context of EEPROM communication.
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* @param addr Address to erase.
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* @return
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* - ESP_OK: on success
|
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* - ESP_ERR_TIMEOUT: if the EEPROM is not able to be ready before the time in the spec. This may mean that the connection is not correct.
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* - or return value from `spi_device_acquire_bus()` `spi_device_polling_transmit()`.
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*/
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esp_err_t spi_eeprom_erase(eeprom_handle_t handle, uint8_t addr);
|
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|
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/**
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* @brief Write a byte into the EEPROM
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*
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||||
* @param handle Context of EEPROM communication.
|
||||
* @param addr Address to write.
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* @param data The byte to write.
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* @return
|
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* - ESP_OK: on success
|
||||
* - ESP_ERR_TIMEOUT: if the EEPROM is not able to be ready before the time in the spec. This may mean that the connection is not correct.
|
||||
* - or return value from `spi_device_acquire_bus()` `spi_device_polling_transmit()`.
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||||
*/
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esp_err_t spi_eeprom_write(eeprom_handle_t handle, uint8_t addr, uint8_t data);
|
||||
|
||||
/**
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||||
* @brief Enable following write/erase to the EEPROM.
|
||||
*
|
||||
* @param handle Context of EEPROM communication.
|
||||
* @return return value from `spi_device_polling_transmit()`.
|
||||
*/
|
||||
esp_err_t spi_eeprom_write_enable(eeprom_handle_t handle);
|
||||
|
||||
/**
|
||||
* @brief Disable following write/erase to the EEPROM.
|
||||
*
|
||||
* @param handle Context of EEPROM communication.
|
||||
* @return return value from `spi_device_polling_transmit()`.
|
||||
*/
|
||||
esp_err_t spi_eeprom_write_disable(eeprom_handle_t handle);
|
||||
|
||||
#if CONFIG_EXAMPLE_5V_COMMANDS
|
||||
/**
|
||||
* @brief Erase all the memory in the EEPROM.
|
||||
*
|
||||
* @note This is only supported when EEPROM VCC is 5V.
|
||||
* @param handle Context of EEPROM communication.
|
||||
* @return
|
||||
* - ESP_OK: on success
|
||||
* - ESP_ERR_TIMEOUT: if the EEPROM is not able to be ready before the time in the spec. This may mean that the connection is not correct.
|
||||
* - or return value from `spi_device_acquire_bus()` `spi_device_polling_transmit()`.
|
||||
*/
|
||||
esp_err_t spi_eeprom_erase_all(eeprom_handle_t handle);
|
||||
|
||||
/**
|
||||
* @brief write all the memory in the EEPROM to the value given.
|
||||
*
|
||||
* @note This is only supported when EEPROM VCC is 5V.
|
||||
* @param handle Context of EEPROM communication.
|
||||
* @return
|
||||
* - ESP_OK: on success
|
||||
* - ESP_ERR_TIMEOUT: if the EEPROM is not able to be ready before the time in the spec. This may mean that the connection is not correct.
|
||||
* - or return value from `spi_device_acquire_bus()` `spi_device_polling_transmit()`.
|
||||
*/
|
||||
esp_err_t spi_eeprom_write_all(eeprom_handle_t handle, uint8_t data);
|
||||
#endif //CONFIG_EXAMPLE_5V_COMMANDS
|
||||
Reference in New Issue
Block a user