driver/i2s: support i2s on c3 and s3

1. Support i2s on esp32c3 and esp32s3 2. Refactor i2s_config_t to avoid breaking change 2. Fix a bug that receiving unavailable values from message queue when dma queue has been re-allocted 4. Support i2s unit test on esp32c3 and esp32s3
2025-08-09 04:25:32 +00:00 · 2021-06-15 15:43:03 +08:00
parent 2f1247e1c4
commit f7f8c9c11f
23 changed files with 1605 additions and 1511 deletions
--- a/components/hal/esp32c3/include/hal/i2s_ll.h
+++ b/components/hal/esp32c3/include/hal/i2s_ll.h
@@ -1,4 +1,4 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.

-// The LL layer for I2C register operations
+// The LL layer for I2S register operations
 /*******************************************************************************
 * NOTICE
 * The hal is not public api, don't use in application code.
@@ -29,14 +29,14 @@ extern "C" {
 #endif


-#define I2S_LL_GET_HW(num) (&I2S0)
-#define I2S_INTR_OUT_DSCR_ERR (0x1 << 6)
-#define I2S_INTR_OUT_EOF      (0x1 << 4)
-#define I2S_INTR_IN_DSCR_ERR  (0x1 << 5)
-#define I2S_INTR_IN_SUC_EOF   (0x1 << 1)
-#define I2S_INTR_MAX          (~0)
+#define I2S_LL_GET_HW(num)             (&I2S0)

-#define I2S_TDM_CH_MASK (0xffff)
+#define I2S_LL_TDM_CH_MASK             (0xffff)
+#define I2S_LL_PDM_BCK_FACTOR          (64)
+#define I2S_LL_BASE_CLK                (2*APB_CLK_FREQ)
+
+#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (9)
+#define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)

 /* I2S clock configuration structure */
 typedef struct {
@@ -44,95 +44,58 @@ typedef struct {
    uint16_t a;
    uint16_t b;        // The decimal part of module clock devider, the decimal is: b/a
    uint16_t bck_div;  // The BCK devider, Fbck = Fmclk / bck_div
-} i2s_clk_cal_t;
-
-/**
- * @brief Calculate the closest sample rate clock configuration.
- *        clock relationship:
- *        Fmclk = bck_div*fbck = fsclk/(mclk_div+b/a)
- *
- * @param fsclk I2S source clock freq.
- * @param fbck BCK freuency.
- * @param bck_div The BCK devider of bck. Generally, set bck_div to 8.
- * @param cal Point to `i2s_clk_cal_t` structure.
- */
-static inline void i2s_ll_clk_cal(uint32_t fsclk, uint32_t fbck, int bck_div, i2s_clk_cal_t *cal)
-{
-    int ma = 0;
-    int mb = 0;
-    uint32_t mclk = fbck*bck_div;
-    cal->mclk_div = fsclk / mclk;
-    cal->bck_div = bck_div;
-    cal->a = 1;
-    cal->b = 0;
-    uint32_t freq_diff = fsclk - mclk * cal->mclk_div;
-    uint32_t min = freq_diff * 512;
-    if (freq_diff == 0) {
-        return;
-    }
-    for (int a = 2; a <= 512; a++) {
-        for (int b = 1; b < a; b++) {
-            ma = freq_diff*a;
-            mb = mclk*b;
-            if (ma == mb) {
-                cal->a = a;
-                cal->b = b;
-                return;
-            }
-            if (abs((mb - ma)) < min) {
-                cal->a = a;
-                cal->b = b;
-                min = abs(mb - ma);
-            }
-        }
-    }
-}
+} i2s_ll_clk_cal_t;

 /**
 * @brief I2S module general init, enable I2S clock.
 *
 * @param hw Peripheral I2S hardware instance address.
 */
-static inline void i2s_ll_general_init(i2s_dev_t *hw)
+static inline void i2s_ll_enable_clock(i2s_dev_t *hw)
 {
    hw->tx_clkm_conf.clk_en = 1;
 }

 /**
- * @brief Reset I2S TX module, enable default source clock and set to TDM mode.
+ * @brief Enable I2S tx module clock
 *
 * @param hw Peripheral I2S hardware instance address.
 */
-static inline void i2s_ll_tx_gen_init(i2s_dev_t *hw)
+static inline void i2s_ll_enable_tx_clock(i2s_dev_t *hw)
 {
-    hw->tx_conf.tx_start = 0;
-    hw->tx_conf.tx_reset = 1;
-    hw->tx_conf.tx_reset = 0;
-    hw->tx_conf.tx_slave_mod = 0;
-    hw->tx_conf.tx_tdm_en = 1;
-    hw->tx_conf.tx_pdm_en = 0;
    hw->tx_clkm_conf.tx_clk_active = 1;
-    hw->tx_clkm_conf.tx_clk_sel = 2;
 }

 /**
- * @brief Reset I2S RX module, enable default source clock and set to TDM mode.
+ * @brief Enable I2S rx module clock
 *
 * @param hw Peripheral I2S hardware instance address.
 */
-static inline void i2s_ll_rx_gen_init(i2s_dev_t *hw)
+static inline void i2s_ll_enable_rx_clock(i2s_dev_t *hw)
 {
-    hw->rx_conf.rx_start = 0;
-    hw->rx_conf.rx_reset = 1;
-    hw->rx_conf.rx_reset = 0;
-    hw->rx_conf.rx_slave_mod = 0;
-    hw->rx_conf.rx_tdm_en = 1;
-    hw->rx_conf.rx_pdm_en = 0;
    hw->rx_clkm_conf.rx_clk_active = 1;
-    hw->rx_clkm_conf.rx_clk_sel = 2;
+}
+
+/**
+ * @brief I2S mclk use tx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_mclk_use_tx_clk(i2s_dev_t *hw)
+{
    hw->rx_clkm_conf.mclk_sel = 0;
 }

+/**
+ * @brief I2S mclk use rx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_mclk_use_rx_clk(i2s_dev_t *hw)
+{
+    hw->rx_clkm_conf.mclk_sel = 1;
+}
+
 /**
 * @brief Enable I2S TX slave mode
 *
@@ -203,7 +166,7 @@ static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw)
 * @brief Set TX source clock
 *
 * @param hw Peripheral I2S hardware instance address.
- * @param src I2S source clock,  ESP32-S3 only support `I2S_CLK_D2CLK`
+ * @param src I2S source clock.
 */
 static inline void i2s_ll_set_tx_clk_src(i2s_dev_t *hw, i2s_clock_src_t src)
 {
@@ -227,27 +190,27 @@ static inline void i2s_ll_set_rx_clk_src(i2s_dev_t *hw, i2s_clock_src_t src)
 * @param hw Peripheral I2S hardware instance address.
 * @param set Pointer to I2S clock devider configuration paramater
 */
-static inline void i2s_ll_set_tx_clk(i2s_dev_t *hw, i2s_clk_cal_t *set)
+static inline void i2s_ll_set_tx_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
 {
    if (set->a == 0 || set->b == 0) {
        hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
        hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
        hw->tx_clkm_div_conf.tx_clkm_div_z = 0;
    } else {
-        if(set->b > set->a/2) {
-            hw->tx_clkm_div_conf.tx_clkm_div_x = set->a/(set->a-set->b) -1;
-            hw->tx_clkm_div_conf.tx_clkm_div_y = set->a%(set->a-set->b);
-            hw->tx_clkm_div_conf.tx_clkm_div_z = set->a-set->b;
+        if (set->b > set->a / 2) {
+            hw->tx_clkm_div_conf.tx_clkm_div_x = set->a / (set->a - set->b) - 1;
+            hw->tx_clkm_div_conf.tx_clkm_div_y = set->a % (set->a - set->b);
+            hw->tx_clkm_div_conf.tx_clkm_div_z = set->a - set->b;
            hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1;
        } else {
-            hw->tx_clkm_div_conf.tx_clkm_div_x = set->a/set->b-1;
-            hw->tx_clkm_div_conf.tx_clkm_div_y = set->a%set->b+1;
+            hw->tx_clkm_div_conf.tx_clkm_div_x = set->a / set->b - 1;
+            hw->tx_clkm_div_conf.tx_clkm_div_y = set->a % set->b + 1;
            hw->tx_clkm_div_conf.tx_clkm_div_z = set->b;
            hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
        }
    }
    hw->tx_clkm_conf.tx_clkm_div_num = set->mclk_div;
-    hw->tx_conf1.tx_bck_div_num = set->bck_div-1;
+    hw->tx_conf1.tx_bck_div_num = set->bck_div - 1;
 }

 /**
@@ -256,27 +219,27 @@ static inline void i2s_ll_set_tx_clk(i2s_dev_t *hw, i2s_clk_cal_t *set)
 * @param hw Peripheral I2S hardware instance address.
 * @param set Pointer to I2S clock devider configuration paramater
 */
-static inline void i2s_ll_set_rx_clk(i2s_dev_t *hw, i2s_clk_cal_t *set)
+static inline void i2s_ll_set_rx_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
 {
    if (set->a == 0 || set->b == 0) {
        hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
        hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
        hw->rx_clkm_div_conf.rx_clkm_div_z = 0;
    } else {
-        if(set->b > set->a/2) {
-            hw->rx_clkm_div_conf.rx_clkm_div_x = set->a/(set->a-set->b)-1;
-            hw->rx_clkm_div_conf.rx_clkm_div_y = set->a%(set->a-set->b);
-            hw->rx_clkm_div_conf.rx_clkm_div_z = set->a-set->b;
+        if (set->b > set->a / 2) {
+            hw->rx_clkm_div_conf.rx_clkm_div_x = set->a / (set->a - set->b) - 1;
+            hw->rx_clkm_div_conf.rx_clkm_div_y = set->a % (set->a - set->b);
+            hw->rx_clkm_div_conf.rx_clkm_div_z = set->a - set->b;
            hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1;
        } else {
-            hw->rx_clkm_div_conf.rx_clkm_div_x = set->a/set->b-1;
-            hw->rx_clkm_div_conf.rx_clkm_div_y = set->a%set->b+1;
+            hw->rx_clkm_div_conf.rx_clkm_div_x = set->a / set->b - 1;
+            hw->rx_clkm_div_conf.rx_clkm_div_y = set->a % set->b + 1;
            hw->rx_clkm_div_conf.rx_clkm_div_z = set->b;
            hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
        }
    }
    hw->rx_clkm_conf.rx_clkm_div_num = set->mclk_div;
-    hw->rx_conf1.rx_bck_div_num = set->bck_div-1;
+    hw->rx_conf1.rx_bck_div_num = set->bck_div - 1;
 }

 /**
@@ -331,7 +294,7 @@ static inline void i2s_ll_stop_rx(i2s_dev_t *hw)
 */
 static inline void i2s_ll_set_tx_tdm_ws_width(i2s_dev_t *hw, int width)
 {
-    hw->tx_conf1.tx_tdm_ws_width = width-1;
+    hw->tx_conf1.tx_tdm_ws_width = width - 1;
 }

 /**
@@ -342,7 +305,7 @@ static inline void i2s_ll_set_tx_tdm_ws_width(i2s_dev_t *hw, int width)
 */
 static inline void i2s_ll_set_rx_tdm_ws_width(i2s_dev_t *hw, int width)
 {
-    hw->rx_conf1.rx_tdm_ws_width = width-1;
+    hw->rx_conf1.rx_tdm_ws_width = width - 1;
 }

 /**
@@ -366,7 +329,7 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, int eof_num)
 static inline void i2s_ll_set_tx_sample_bit(i2s_dev_t *hw, uint8_t sample_bit, int data_bit)
 {
    hw->tx_conf1.tx_bits_mod = data_bit - 1;
-    hw->tx_conf1.tx_tdm_chan_bits = sample_bit-1;
+    hw->tx_conf1.tx_tdm_chan_bits = sample_bit - 1;
 }

 /**
@@ -379,7 +342,7 @@ static inline void i2s_ll_set_tx_sample_bit(i2s_dev_t *hw, uint8_t sample_bit, i
 static inline void i2s_ll_set_rx_sample_bit(i2s_dev_t *hw, uint8_t sample_bit, int data_bit)
 {
    hw->rx_conf1.rx_bits_mod = data_bit - 1;
-    hw->rx_conf1.rx_tdm_chan_bits = sample_bit-1;
+    hw->rx_conf1.rx_tdm_chan_bits = sample_bit - 1;
 }

 /**
@@ -390,7 +353,7 @@ static inline void i2s_ll_set_rx_sample_bit(i2s_dev_t *hw, uint8_t sample_bit, i
 */
 static inline void i2s_ll_set_tx_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
 {
-    hw->tx_conf1.tx_half_sample_bits = half_sample_bits-1;
+    hw->tx_conf1.tx_half_sample_bits = half_sample_bits - 1;
 }

 /**
@@ -401,7 +364,7 @@ static inline void i2s_ll_set_tx_half_sample_bit(i2s_dev_t *hw, int half_sample_
 */
 static inline void i2s_ll_set_rx_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
 {
-    hw->rx_conf1.rx_half_sample_bits = half_sample_bits-1;
+    hw->rx_conf1.rx_half_sample_bits = half_sample_bits - 1;
 }

 /**
@@ -432,9 +395,9 @@ static inline void i2s_ll_rx_msb_shift_enable(i2s_dev_t *hw, bool msb_shift_enab
 * @param hw Peripheral I2S hardware instance address.
 * @param total_num Total slot number
 */
-static inline void i2s_ll_set_tx_slot_mun(i2s_dev_t *hw, int total_num)
+static inline void i2s_ll_set_tx_slot_num(i2s_dev_t *hw, int total_num)
 {
-    hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = total_num-1;
+    hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = total_num - 1;
 }

 /**
@@ -443,22 +406,22 @@ static inline void i2s_ll_set_tx_slot_mun(i2s_dev_t *hw, int total_num)
 * @param hw Peripheral I2S hardware instance address.
 * @param total_num Total slot number
 */
-static inline void i2s_ll_set_rx_slot_mun(i2s_dev_t *hw, int total_num)
+static inline void i2s_ll_set_rx_slot_num(i2s_dev_t *hw, int total_num)
 {
-    hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num-1;
+    hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1;
 }

 /**
 * @brief Set the bimap of the active TX slot, only the active slot can launch audio data.
 *
 * @param hw Peripheral I2S hardware instance address.
- * @param
+ * @param slot_mask mask of tx active slot
 */
 static inline void i2s_ll_set_tx_active_slot_mask(i2s_dev_t *hw, uint32_t slot_mask)
 {
    typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= slot_mask&I2S_TDM_CH_MASK;
+    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
+    tdm_ctrl_reg.val |= slot_mask & I2S_LL_TDM_CH_MASK;
    hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
 }

@@ -466,13 +429,13 @@ static inline void i2s_ll_set_tx_active_slot_mask(i2s_dev_t *hw, uint32_t slot_m
 * @brief Set the bimap of the active RX slot, only the active slot can receive audio data.
 *
 * @param hw Peripheral I2S hardware instance address.
- * @param
+ * @param slot_mask mask of rx active slot
 */
 static inline void i2s_ll_set_rx_active_slot_mask(i2s_dev_t *hw, uint32_t slot_mask)
 {
    typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= slot_mask&I2S_TDM_CH_MASK;
+    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
+    tdm_ctrl_reg.val |= slot_mask & I2S_LL_TDM_CH_MASK;
    hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
 }

@@ -480,7 +443,7 @@ static inline void i2s_ll_set_rx_active_slot_mask(i2s_dev_t *hw, uint32_t slot_m
 * @brief Set TX WS signal pol level
 *
 * @param hw Peripheral I2S hardware instance address.
- * @param
+ * @param ws_pol_level pin level of WS(output) when receiving left channel data
 */
 static inline void i2s_set_tx_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
 {
@@ -491,7 +454,7 @@ static inline void i2s_set_tx_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
 * @brief Set RX WS signal pol level
 *
 * @param hw Peripheral I2S hardware instance address.
- * @param
+ * @param ws_pol_level pin level of WS(input) when receiving left channel data
 */
 static inline void i2s_set_rx_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
 {
@@ -533,7 +496,7 @@ static inline void i2s_ll_tx_pdm_cfg(i2s_dev_t *hw, uint32_t sample_rate)
    pdm_conf_reg.tx_pdm_lp_in_shift = 1;
    pdm_conf_reg.tx_pdm_sinc_in_shift = 1;
    pdm_conf_reg.tx_pdm_sigmadelta_in_shift = 1;
-    pdm_conf_reg.tx_pdm_sinc_osr2 =  fp/fs;
+    pdm_conf_reg.tx_pdm_sinc_osr2 =  fp / fs;
    pdm_conf_reg.tx_pdm_dac_mode_en =  1;
    pdm_conf_reg.tx_pdm_sigmadelta_dither = 0;
    pdm_conf_reg.tx_pdm_sigmadelta_dither2 = 0;
@@ -541,7 +504,7 @@ static inline void i2s_ll_tx_pdm_cfg(i2s_dev_t *hw, uint32_t sample_rate)
    pdm_conf1_reg.tx_pdm_fp = fp;
    pdm_conf1_reg.tx_pdm_fs = fs;
    pdm_conf1_reg.tx_iir_hp_mult12_5 = 7;
-    pdm_conf1_reg.tx_iir_hp_mult12_0 =6;
+    pdm_conf1_reg.tx_iir_hp_mult12_0 = 6;
    pdm_conf_reg.tx_pdm_hp_bypass = 0;
    hw->tx_pcm2pdm_conf = pdm_conf_reg;
    hw->tx_pcm2pdm_conf1 = pdm_conf1_reg;
@@ -583,13 +546,8 @@ static inline void i2s_ll_get_tx_pdm_fpfs(i2s_dev_t *hw, uint32_t *fp, uint32_t
 */
 static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool pdm_enable)
 {
-    if (pdm_enable) {
-        hw->rx_conf.rx_tdm_en = 0;
-        hw->rx_conf.rx_pdm_en = 1;
-    } else {
-        hw->rx_conf.rx_pdm_en = 0;
-        hw->rx_conf.rx_tdm_en = 1;
-    }
+    hw->rx_conf.rx_pdm_en = pdm_enable;
+    hw->rx_conf.rx_tdm_en = !pdm_enable;
 }

 /**
@@ -598,7 +556,7 @@ static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool pdm_enable)
 * @param hw Peripheral I2S hardware instance address.
 * @param pcm_cfg PCM configuration paramater
 */
-static inline void i2s_ll_tx_pcm_cfg(i2s_dev_t *hw, i2s_pcm_cfg_t pcm_cfg)
+static inline void i2s_ll_tx_pcm_cfg(i2s_dev_t *hw, i2s_pcm_mode_t pcm_cfg)
 {
    if (pcm_cfg == I2S_PCM_DISABLE) {
        hw->tx_conf.tx_pcm_bypass = 1;
@@ -614,7 +572,7 @@ static inline void i2s_ll_tx_pcm_cfg(i2s_dev_t *hw, i2s_pcm_cfg_t pcm_cfg)
 * @param hw Peripheral I2S hardware instance address.
 * @param pcm_cfg PCM configuration paramater
 */
-static inline void i2s_ll_rx_pcm_cfg(i2s_dev_t *hw, i2s_pcm_cfg_t pcm_cfg)
+static inline void i2s_ll_rx_pcm_cfg(i2s_dev_t *hw, i2s_pcm_mode_t pcm_cfg)
 {
    if (pcm_cfg == I2S_PCM_DISABLE) {
        hw->rx_conf.rx_pcm_bypass = 1;
@@ -690,6 +648,18 @@ static inline void i2s_ll_rx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena)
    hw->rx_conf.rx_bit_order = lsb_order_ena;
 }

+/**
+ * @brief Configure TX skip mask enable
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param skip_mask_ena Set true to skip inactive channels.
+ */
+static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
+{
+    hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
+}
+
+
 /**
 * @brief Configure single data
 *