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driver/i2s: support i2s on c3 and s3

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1. Support i2s on esp32c3 and esp32s3
    2. Refactor i2s_config_t to avoid breaking change
    2. Fix a bug that receiving unavailable values from message queue when dma queue has been re-allocted
    4. Support i2s unit test on esp32c3 and esp32s3
This commit is contained in:
laokaiyao
2021-06-15 15:43:03 +08:00
parent 2f1247e1c4
commit f7f8c9c11f
23 changed files with 1605 additions and 1511 deletions
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1
components/soc/esp32c3/i2s_periph.c
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@@ -26,7 +26,6 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.rx_ws_sig = I2SI_WS_IN_IDX,
.data_out_sig = I2SO_SD_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_DMA_CH0_INTR_SOURCE,
.module = PERIPH_I2S1_MODULE,
}
};

6
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -109,7 +109,11 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_RX (0)
#define SOC_I2S_SUPPORTS_PDM (1) //(SOC_I2S_SUPPORTS_PDM_RX | SOC_I2S_SUPPORTS_PDM_TX)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware