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docs: provide CN translation for api-reference/peripherals/sdmmc_host.rst
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caixinying-git
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SDMMC Host Driver
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=================
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:link_to_translation:`zh_CN:[中文]`
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Overview
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--------
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{IDF_TARGET_NAME}'s SDMMC host peripheral has two slots. Each slot can be used independently to connect to an SD card, SDIO device or eMMC chip.
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{IDF_TARGET_NAME}'s SDMMC host peripheral has two slots. Each slot can be used independently to connect to an SD card, SDIO device, or eMMC chip.
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.. only:: esp32
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@@ -13,44 +15,61 @@ Overview
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The slots are connected to {IDF_TARGET_NAME} GPIOs using IO MUX. Pin mappings of these slots are given in the table below.
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+--------+-------------+-------------+
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| Signal | Slot 0 | Slot 1 |
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+========+=============+=============+
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| CMD | GPIO11 | GPIO15 |
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+--------+-------------+-------------+
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| CLK | GPIO6 | GPIO14 |
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+--------+-------------+-------------+
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| D0 | GPIO7 | GPIO2 |
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+--------+-------------+-------------+
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| D1 | GPIO8 | GPIO4 |
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+--------+-------------+-------------+
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| D2 | GPIO9 | GPIO12 |
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+--------+-------------+-------------+
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| D3 | GPIO10 | GPIO13 |
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+--------+-------------+-------------+
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| D4 | GPIO16 | |
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+--------+-------------+-------------+
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| D5 | GPIO17 | |
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+--------+-------------+-------------+
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| D6 | GPIO5 | |
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+--------+-------------+-------------+
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| D7 | GPIO18 | |
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+--------+-------------+-------------+
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| CD | any input via GPIO matrix |
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+--------+---------------------------+
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| WP | any input via GPIO matrix |
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+--------+---------------------------+
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.. list-table::
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:header-rows: 1
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:widths: 20 40 40
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:align: center
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The Card Detect and Write Protect signals can be routed to arbitrary pins using the GPIO matrix. To reserve the pins, set the ``cd`` and ``wp`` members of the :cpp:class:`sdmmc_slot_config_t` structure before calling :cpp:func:`sdmmc_host_init_slot`. Please note that it is not advised to specify a Card Detect pin when working with SDIO cards, because the card detect signal in ESP32 can also trigger SDIO slave interrupt.
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* - Signal
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- Slot 0
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- Slot 1
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* - CMD
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- GPIO11
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- GPIO15
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* - CLK
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- GPIO6
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- GPIO14
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* - D0
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- GPIO7
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- GPIO2
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* - D1
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- GPIO8
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- GPIO4
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* - D2
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- GPIO9
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- GPIO12
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* - D3
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- GPIO10
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- GPIO13
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* - D4
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- GPIO16
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-
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* - D5
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- GPIO17
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-
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* - D6
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- GPIO5
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-
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* - D7
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- GPIO18
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-
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* - CD
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- any input via GPIO matrix
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- any input via GPIO matrix
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* - WP
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- any input via GPIO matrix
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- any input via GPIO matrix
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The Card Detect (CD) and Write Protect (WP) signals can be routed to arbitrary pins using the GPIO matrix. To reserve the pins, set the ``cd`` and ``wp`` members of the :cpp:class:`sdmmc_slot_config_t` structure before calling :cpp:func:`sdmmc_host_init_slot`. Please note that it is not advised to specify a CD pin when working with SDIO cards, because the CD signal in ESP32 can also trigger SDIO slave interrupt.
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.. warning::
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Pins used by Slot 0 (``HS1_*``) are also used to connect the SPI flash chip in ESP32-WROOM and ESP32-WROVER modules. These pins cannot be shared between an SD card and SPI flash. If you need to use Slot 0, connect SPI flash to different pins and set eFuses accordingly.
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Pins used by Slot 0 (``HS1_*``) are also used to connect the SPI flash chip in ESP32-WROOM and ESP32-WROVER modules. These pins cannot be concurrently shared between an SD card and an SPI flash. If you need to use Slot 0, establish an alternative connection for the SPI flash using different pins and configure the necessary eFuses accordingly.
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.. only:: SOC_SDMMC_USE_GPIO_MATRIX
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Both slots (:c:macro:`SDMMC_HOST_SLOT_0`, :c:macro:`SDMMC_HOST_SLOT_1`) support 1-, 4- and 8-line SD interface. The slots are connected to {IDF_TARGET_NAME} GPIOs using GPIO matrix. This means that any GPIO may be used for each of the SD card signals.
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Both slots :c:macro:`SDMMC_HOST_SLOT_0` and :c:macro:`SDMMC_HOST_SLOT_1` support 1-, 4- and 8-line SD interfaces. The slots are connected to {IDF_TARGET_NAME} GPIOs using the GPIO matrix. This means that any GPIO may be used for each of the SD card signals.
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Supported Speed Modes
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@@ -58,14 +77,14 @@ Supported Speed Modes
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SDMMC Host driver supports the following speed modes:
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- Default Speed (20 MHz), 1-line or 4-line (with SD cards), and 1-line, 4-line or 8-line (with 3.3 V eMMC)
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- High Speed (40 MHz), 1-line or 4-line (with SD cards), and 1-line, 4-line or 8-line (with 3.3 V eMMC)
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- High Speed DDR (40 MHz), 4-line (with 3.3 V eMMC)
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- Default Speed (20 MHz): 1-line or 4-line with SD cards, and 1-line, 4-line, or 8-line with 3.3 V eMMC
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- High Speed (40 MHz): 1-line or 4-line with SD cards, and 1-line, 4-line, or 8-line with 3.3 V eMMC
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- High Speed DDR (40 MHz): 4-line with 3.3 V eMMC
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Speed modes not supported at present:
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- High Speed DDR mode, 8-line eMMC
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- UHS-I 1.8 V modes, 4-line SD cards
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- High Speed DDR mode: 8-line eMMC
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- UHS-I 1.8 V modes: 4-line SD cards
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Using the SDMMC Host Driver
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@@ -87,17 +106,22 @@ Other functions, such as the ones given below, will be called by the SD/MMC prot
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Configuring Bus Width and Frequency
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-----------------------------------
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With the default initializers for :cpp:class:`sdmmc_host_t` and :cpp:class:`sdmmc_slot_config_t` (:c:macro:`SDMMC_HOST_DEFAULT` and :c:macro:`SDMMC_SLOT_CONFIG_DEFAULT`), SDMMC Host driver will attempt to use the widest bus supported by the card (4 lines for SD, 8 lines for eMMC) and the frequency of 20 MHz.
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With the default initializers for :cpp:class:`sdmmc_host_t` and :cpp:class:`sdmmc_slot_config_t`, i.e., :c:macro:`SDMMC_HOST_DEFAULT` and :c:macro:`SDMMC_SLOT_CONFIG_DEFAULT`, SDMMC Host driver will attempt to use the widest bus supported by the card (4 lines for SD, 8 lines for eMMC) and the frequency of 20 MHz.
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In the designs where communication at 40 MHz frequency can be achieved, it is possible to increase the bus frequency by changing the ``max_freq_khz`` field of :cpp:class:`sdmmc_host_t`::
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In the designs where communication at 40 MHz frequency can be achieved, it is possible to increase the bus frequency by changing the ``max_freq_khz`` field of :cpp:class:`sdmmc_host_t`:
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.. code-block::
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sdmmc_host_t host = SDMMC_HOST_DEFAULT();
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host.max_freq_khz = SDMMC_FREQ_HIGHSPEED;
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If you need a specific frequency other than standard speeds, you are free to use any value from within appropriate range of the SD interface given (SDMMC or SDSPI). However, the real clock frequency shall be calculated by the underlying driver and the value can be different from the one required.
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For the SDMMC, ``max_freq_khz`` works as the upper limit so the final frequency value shall be always lower or equal. For the SDSPI, the nearest fitting frequency is supplied and thus the value can be greater than / equal to / lower than ``max_freq_khz``.
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If you need a specific frequency other than standard speeds, you are free to use any value from within an appropriate range of the SD interface given (SDMMC or SDSPI). However, the real clock frequency shall be calculated by the underlying driver and the value can be different from the one required.
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To configure the bus width, set the ``width`` field of :cpp:class:`sdmmc_slot_config_t`. For example, to set 1-line mode::
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For the SDMMC, ``max_freq_khz`` works as the upper limit so the final frequency value shall be always lower or equal. For the SDSPI, the nearest fitting frequency is supplied and thus the value can be greater than/equal to/lower than ``max_freq_khz``.
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To configure the bus width, set the ``width`` field of :cpp:class:`sdmmc_slot_config_t`. For example, to set 1-line mode:
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.. code-block::
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sdmmc_slot_config_t slot = SDMMC_SLOT_CONFIG_DEFAULT();
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slot.width = 1;
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@@ -107,7 +131,11 @@ To configure the bus width, set the ``width`` field of :cpp:class:`sdmmc_slot_co
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Configuring GPIOs
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-----------------
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{IDF_TARGET_NAME} SDMMC Host can be configured to use arbitrary GPIOs for each of the signals. Configuration is performed by setting members of :cpp:class:`sdmmc_slot_config_t` structure. For example, to use GPIOs 1-6 for CLK, CMD, D0 - D3 signals, respectively::
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{IDF_TARGET_NAME} SDMMC Host can be configured to use arbitrary GPIOs for each of the signals. Configuration is performed by setting members of :cpp:class:`sdmmc_slot_config_t` structure.
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For example, to use GPIOs 1-6 for CLK, CMD, and D0-D3 signals respectively:
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.. code-block::
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sdmmc_slot_config_t slot = SDMMC_SLOT_CONFIG_DEFAULT();
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slot.clk = GPIO_NUM_1;
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@@ -117,16 +145,18 @@ To configure the bus width, set the ``width`` field of :cpp:class:`sdmmc_slot_co
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slot.d2 = GPIO_NUM_5;
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slot.d3 = GPIO_NUM_6;
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It is also possible to configure Card Detect and Write Protect pins. Similar to other signals, set ``cd`` and ``wp`` members of the same structure::
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It is also possible to configure Card Detect and Write Protect pins. Similar to other signals, set ``cd`` and ``wp`` members of the same structure:
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.. code-block::
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slot.cd = GPIO_NUM_7;
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slot.wp = GPIO_NUM_8;
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``SDMMC_SLOT_CONFIG_DEFAULT`` sets both to ``GPIO_NUM_NC``, meaning that by default the signals are not used.
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Once :cpp:class:`sdmmc_slot_config_t` structure is initialized this way, you can use it when calling :cpp:func:`sdmmc_host_init_slot` or one of the higher level functions, such as :cpp:func:`esp_vfs_fat_sdmmc_mount`.
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Once :cpp:class:`sdmmc_slot_config_t` structure is initialized this way, you can use it when calling :cpp:func:`sdmmc_host_init_slot` or one of the higher level functions (such as :cpp:func:`esp_vfs_fat_sdmmc_mount`).
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DDR Mode for eMMC chips
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DDR Mode for eMMC Chips
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-----------------------
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By default, DDR mode will be used if:
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@@ -134,7 +164,9 @@ By default, DDR mode will be used if:
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- SDMMC host frequency is set to :c:macro:`SDMMC_FREQ_HIGHSPEED` in :cpp:class:`sdmmc_host_t` structure, and
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- eMMC chip reports DDR mode support in its CSD register
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DDR mode places higher requirements for signal integrity. To disable DDR mode while keeping :c:macro:`SDMMC_FREQ_HIGHSPEED` frequency, clear :c:macro:`SDMMC_HOST_FLAG_DDR` bit in ``flags`` field of :cpp:class:`sdmmc_host_t`::
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DDR mode places higher requirements for signal integrity. To disable DDR mode while keeping the :c:macro:`SDMMC_FREQ_HIGHSPEED` frequency, clear the :c:macro:`SDMMC_HOST_FLAG_DDR` bit in :cpp:member:`sdmmc_host_t::flags` field of the :cpp:class:`sdmmc_host_t`:
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.. code-block::
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sdmmc_host_t host = SDMMC_HOST_DEFAULT();
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host.max_freq_khz = SDMMC_FREQ_HIGHSPEED;
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@@ -144,11 +176,9 @@ DDR mode places higher requirements for signal integrity. To disable DDR mode wh
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See also
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--------
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See :doc:`SD/SDIO/MMC Driver <../storage/sdmmc>` for the higher level driver which implements the protocol layer.
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See :doc:`SD SPI Host Driver <sdspi_host>` for a similar driver which uses the SPI controller and is limited to SD protocol's SPI mode.
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See :doc:`sd_pullup_requirements` for pullup support and compatibilities of modules and development kits.
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- :doc:`../storage/sdmmc`: introduces the higher-level driver which implements the protocol layer.
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- :doc:`sdspi_host`: introduces a similar driver that uses the SPI controller and is limited to SD protocol's SPI mode.
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- :doc:`sd_pullup_requirements`: introduces pull-up support and compatibilities of modules and development kits.
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API Reference
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