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refactor (soc, esp_rom)!: removed target-specific ROM dependencies

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This commit is contained in:
Jakob Hasse
2022-05-23 16:23:07 +08:00
parent fca7be2ddb
commit f8b5ed5d6c
12 changed files with 84 additions and 243 deletions
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4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@@ -203,6 +203,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CACHE_MEMORY_IBANK_SIZE
hex
default 0x4000
config SOC_CPU_CORES_NUM
int
default 1

4
components/soc/esp32c3/include/soc/memprot_defs.h
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@@ -7,8 +7,8 @@
#pragma once
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/sensitive_reg.h"
#include "esp32c3/rom/cache.h"
#ifdef __cplusplus
extern "C" {
@@ -39,7 +39,7 @@ typedef union {
//16kB (ICACHE)
#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000
#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + SOC_CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
//128kB (LEVEL 1)
#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000

1
components/soc/esp32c3/include/soc/soc_caps.h
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@@ -100,6 +100,7 @@
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
#define SOC_CACHE_MEMORY_IBANK_SIZE 0x4000 // has to be same as the definition in ROM component
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_CORES_NUM (1U)