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esp32c2: support rtc time feature depend on rtc memory, since c2 does not have rtc memory

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This commit is contained in:
jingli
2022-07-13 21:10:17 +08:00
parent fb1902773f
commit f8cc2ec86d
7 changed files with 80 additions and 108 deletions
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18
components/esp_rom/include/esp32c2/rom/rtc.h
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@@ -45,29 +45,35 @@ extern "C" {
*
*************************************************************************************
* RTC store registers usage
* RTC_CNTL_STORE0_REG Reserved
* RTC_CNTL_STORE0_REG RTC fix us, high 32 bits
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
* RTC_CNTL_STORE6_REG rtc reset cause
* RTC_CNTL_STORE7_REG RTC fix us, low 32 bits
*************************************************************************************
*
* Since esp32c2 does not support RTC fast mem, so use RTC store regs to record rtc time:
*
* |------------------------|----------------------------------------|
* | RTC_CNTL_STORE0_REG | RTC_CNTL_STORE7_REG |
* | rtc_fix_us(MSB) | rtc_fix_us(LSB) |
* |------------------------|----------------------------------------|
*/
#define RTC_FIX_US_HIGH_REG RTC_CNTL_STORE0_REG
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define RTC_FIX_US_LOW_REG RTC_CNTL_STORE7_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
typedef enum {
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.