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Merge branch 'docs/add_flash_to_psram_feature' into 'master'

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docs: add the flash content moved to psram feature

Closes IDF-5885

See merge request espressif/esp-idf!19908
This commit is contained in:
Wan Lei
2022-10-17 14:51:15 +08:00
parent faff090d5a 76eef386bb
commit f98a37f571
10 changed files with 113 additions and 31 deletions
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21
docs/en/api-reference/storage/spi_flash_concurrency.rst
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@@ -5,7 +5,7 @@ Concurrency Constraints for flash on SPI1
The SPI0/1 bus is shared between the instruction & data cache (for firmware execution) and the SPI1 peripheral (controlled by the drivers including this SPI Flash driver). Hence, operations to SPI1 will cause significant influence to the whole system. This kind of operations include calling SPI Flash API or other drivers on SPI1 bus, any operations like read/write/erase or other user defined SPI operations, regardless to the main flash or other SPI slave devices.
.. only:: not esp32c3
.. only:: not (esp32c3 or SOC_SPIRAM_XIP_SUPPORTED)
On {IDF_TARGET_NAME}, these caches must be disabled while reading/writing/erasing.
@@ -15,6 +15,11 @@ The SPI0/1 bus is shared between the instruction & data cache (for firmware exec
If this option is disabled, the caches must be disabled while reading/writing/erasing operations. There are some constraints using driver on the SPI1 bus, see :ref:`impact_disabled_cache`. This constraints will cause more IRAM/DRAM usages.
.. only:: SOC_SPIRAM_XIP_SUPPORTED
On {IDF_TARGET_NAME}, the config option :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` (disabled by default) and :ref:`CONFIG_SPIRAM_RODATA` (disabled by default) allow the cache to read/write PSRAM concurrently with SPI1 operations. See :ref:`xip_from_psram` for more details.
If this option is disabled, the caches must be disabled while reading/writing/erasing operations. There are some constraints using driver on the SPI1 bus, see :ref:`impact_disabled_cache`. This constraints will cause more IRAM/DRAM usages.
.. _impact_disabled_cache:
@@ -25,7 +30,15 @@ Under this condition, all CPUs should always execute code and access data from i
.. only:: esp32c3
However, when :ref:`CONFIG_SPI_FLASH_AUTO_SUSPEND` is enabled, these APIs won't disable the caches. The hardware will handle the arbitration between them.
.. note::
When :ref:`CONFIG_SPI_FLASH_AUTO_SUSPEND` is enabled, these APIs won't disable the caches. The hardware will handle the arbitration between them.
.. only:: SOC_SPIRAM_XIP_SUPPORTED
.. note::
When :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` and :ref:`CONFIG_SPIRAM_RODATA` are both enabled, these APIs won't disable the caches.
.. only:: not CONFIG_FREERTOS_UNICORE
@@ -66,3 +79,7 @@ If the ``ESP_INTR_FLAG_IRAM`` flag is not set when registering, the interrupt ha
.. only:: esp32c3
.. include:: auto_suspend.inc
.. only:: SOC_SPIRAM_XIP_SUPPORTED
.. include:: xip_from_psram.inc

12
docs/en/api-reference/storage/xip_from_psram.inc Normal file
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@@ -0,0 +1,12 @@
.. _xip_from_psram:
XIP from PSRAM Feature
----------------------
If :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` is enabled, the flash ``.text`` sections (used for instructions) will be placed in PSRAM.
If :ref:`CONFIG_SPIRAM_RODATA` is enabled, the flash ``.rodata`` sections (used for read only data) will be placed in PSRAM.
The corresponding virtual memory range will be re-mapped to PSRAM.
If both of the above options are enabled, the Cache won't be disabled during an SPI1 Flash operation. You don't need to make sure ISRs, ISR callbacks and involved data are placed in internal RAM.