mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-08 04:02:27 +00:00
Update LEDC, PCNT,Timer_Group driver for esp32s2beta.
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@@ -1,4 +1,4 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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@@ -19,6 +19,7 @@
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#include "freertos/xtensa_api.h"
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#include "driver/timer.h"
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#include "driver/periph_ctrl.h"
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#include "soc/rtc.h"
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#include "sdkconfig.h"
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static const char* TIMER_TAG = "timer_group";
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@@ -48,9 +49,9 @@ esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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TIMER_CHECK(timer_val != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
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portENTER_CRITICAL_SAFE(&timer_spinlock[group_num]);
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#if CONFIG_IDF_TARGET_ESP32
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#ifdef CONFIG_IDF_TARGET_ESP32
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TG[group_num]->hw_timer[timer_num].update = 1;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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TG[group_num]->hw_timer[timer_num].update.update = 1;
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#endif
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*timer_val = ((uint64_t) TG[group_num]->hw_timer[timer_num].cnt_high << 32)
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@@ -69,7 +70,15 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
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esp_err_t err = timer_get_counter_value(group_num, timer_num, &timer_val);
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if (err == ESP_OK) {
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uint16_t div = TG[group_num]->hw_timer[timer_num].config.divider;
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#ifdef CONFIG_IDF_TARGET_ESP32
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*time = (double)timer_val * div / TIMER_BASE_CLK;
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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if(TG[group_num]->hw_timer[timer_num].config.use_xtal) {
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*time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000);
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} else {
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*time = (double)timer_val * div / rtc_clk_apb_freq_get();
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}
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#endif
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}
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return err;
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}
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@@ -227,9 +236,9 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
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//but software reset does not clear interrupt status. This is not safe for application when enable the interrupt of timer_group.
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//we need to disable the interrupt and clear the interrupt status here.
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TG[group_num]->int_ena.val &= (~BIT(timer_num));
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#if CONFIG_IDF_TARGET_ESP32
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#ifdef CONFIG_IDF_TARGET_ESP32
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TG[group_num]->int_clr_timers.val = BIT(timer_num);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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TG[group_num]->int_clr.val = BIT(timer_num);
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#endif
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TG[group_num]->hw_timer[timer_num].config.autoreload = config->auto_reload;
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@@ -239,6 +248,9 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
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TG[group_num]->hw_timer[timer_num].config.alarm_en = config->alarm_en;
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TG[group_num]->hw_timer[timer_num].config.level_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 1 : 0);
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TG[group_num]->hw_timer[timer_num].config.edge_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 0 : 1);
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#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
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TG[group_num]->hw_timer[timer_num].config.use_xtal = config->clk_sel;
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#endif
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TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
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return ESP_OK;
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}
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@@ -293,5 +305,3 @@ esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
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TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
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return timer_group_intr_disable(group_num, BIT(timer_num));
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}
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