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dac: update unit-test docs and examples for driver-NG

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This commit is contained in:
laokaiyao
2022-05-24 17:26:36 +08:00
parent 351a18415c
commit f9f9a09dfb
129 changed files with 4163 additions and 8227 deletions
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99
components/hal/esp32s2/dac_hal.c
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@@ -1,99 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for ADC (esp32s2 specific part)
#include "hal/dac_hal.h"
#include "hal/adc_ll.h"
#include "hal/dac_types.h"
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
#define dac_ll_dma_clear_intr(dev, mask) spi_ll_clear_intr(dev, mask)
#define dac_ll_dma_enable_intr(dev, mask) spi_ll_enable_intr(dev, mask)
#define dac_ll_dma_fifo_reset(dev) spi_ll_dma_tx_fifo_reset(dev)
#define dac_ll_dma_disable_intr(dev, mask) spi_ll_disable_intr(dev, mask)
#define dac_ll_dma_get_intr(dev, mask) spi_ll_get_intr(dev, mask)
#define dac_ll_dma_disable(dev) spi_dma_ll_tx_disable(dev)
#define dac_ll_dma_reset(dev, chan) spi_dma_ll_tx_reset(dev, chan)
#define dac_ll_dma_start(dev, chan, desc) spi_dma_ll_tx_start(dev, chan, desc)
void dac_dma_hal_clr_intr(dac_hal_context_t *hal)
{
spi_ll_clear_intr(hal->dev, DAC_DMA_HAL_INTR);
}
bool dac_dma_hal_get_intr_status(dac_hal_context_t *hal)
{
return spi_ll_get_intr(hal->dev, DAC_DMA_HAL_INTR);
}
void dac_dma_hal_init(dac_hal_context_t *hal)
{
dac_ll_dma_clear_intr(hal->dev, DAC_DMA_HAL_INTR);
dac_ll_dma_enable_intr(hal->dev, DAC_DMA_HAL_INTR);
}
void dac_dma_hal_deinit(dac_hal_context_t *hal)
{
dac_ll_digi_trigger_output(false);
dac_ll_digi_enable_dma(false);
dac_ll_dma_clear_intr(hal->dev, DAC_DMA_HAL_INTR);
dac_ll_dma_disable(hal->dev);
}
void dac_dma_hal_trans_start(dac_hal_context_t *hal, lldesc_t *desc)
{
dac_ll_dma_reset(hal->dev, hal->dma_chan);
dac_ll_dma_fifo_reset(hal->dev);
dac_ll_dma_start(hal->dev, hal->dma_chan, desc);
}
void dac_hal_digi_controller_configure(const dac_hal_ctrl_config_t *cfg)
{
dac_ll_digi_clk_inv(true);
dac_ll_digi_set_convert_mode(cfg->mode == DAC_CONV_ALTER);
dac_ll_digi_set_trigger_interval(cfg->interval);
adc_ll_digi_controller_clk_div(cfg->dig_clk.div_num, cfg->dig_clk.div_b, cfg->dig_clk.div_a);
adc_ll_digi_clk_sel(cfg->dig_clk.use_apll);
}
void dac_hal_digi_start(void)
{
dac_ll_digi_enable_dma(true);
dac_ll_digi_trigger_output(true);
}
void dac_hal_digi_stop(void)
{
dac_ll_digi_trigger_output(false);
dac_ll_digi_enable_dma(false);
}
void __attribute__((deprecated)) dac_hal_digi_deinit(void)
{
dac_ll_digi_trigger_output(false);
dac_ll_digi_enable_dma(false);
dac_ll_digi_fifo_reset();
dac_ll_digi_reset();
}
void __attribute__((deprecated)) dac_hal_digi_controller_config(const dac_digi_config_t *cfg)
{
dac_ll_digi_set_convert_mode(cfg->mode == DAC_CONV_ALTER);
dac_ll_digi_set_trigger_interval(cfg->interval);
adc_ll_digi_controller_clk_div(cfg->dig_clk.div_num, cfg->dig_clk.div_b, cfg->dig_clk.div_a);
adc_ll_digi_controller_clk_enable(cfg->dig_clk.use_apll);
}
void __attribute__((deprecated)) dac_hal_digi_init(void)
{
dac_ll_digi_clk_inv(true);
}

128
components/hal/esp32s2/include/hal/dac_hal.h
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@@ -1,128 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for DAC (esp32s2 specific part)
#pragma once
#include "hal/dac_ll.h"
#include "hal/dac_types.h"
#include "hal/spi_ll.h"
#include "soc/lldesc.h"
#include_next "hal/dac_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DAC_DMA_HAL_INTR (SPI_LL_INTR_OUT_TOTAL_EOF)
typedef struct {
void *dev;
uint32_t dma_chan;
} dac_hal_context_t;
typedef struct {
dac_digi_convert_mode_t mode;
uint32_t interval;
} dac_hal_ctrl_config_t;
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* Digital controller initialization.
*/
void dac_hal_digi_init(void);
/**
* Digital controller deinitialization.
*/
void dac_hal_digi_deinit(void);
/**
* Setting the DAC digital controller.
*
* @param cfg Pointer to digital controller paramter.
*/
void dac_hal_digi_controller_configure(const dac_hal_ctrl_config_t *ctrl_cfg);
/**
* DAC digital controller start output voltage.
*/
void dac_hal_digi_start(void);
/**
* DAC digital controller stop output voltage.
*/
void dac_hal_digi_stop(void);
/**
* Reset DAC digital controller FIFO.
*/
#define dac_hal_digi_fifo_reset() dac_ll_digi_fifo_reset()
/**
* Reset DAC digital controller.
*/
#define dac_hal_digi_reset() dac_ll_digi_reset()
/*******************************************************
* DAC-DMA hal layer functions.
* On ESP32-S2, DAC shares the DMA with SPI3.
*******************************************************/
/**
* DAC DMA HAL initialization
*
* @param hal Context of the HAL layer
*/
void dac_dma_hal_init(dac_hal_context_t *hal);
/**
* DAC DMA HAL interrupt clear.
*
* @param hal Context of the HAL layer
*/
void dac_dma_hal_clr_intr(dac_hal_context_t *hal);
/**
* DAC DMA HAL transaction start.
*
* @param hal Context of the HAL layer
*/
void dac_dma_hal_trans_start(dac_hal_context_t *hal, lldesc_t *desc);
/**
* Get if interrupt is triggered or not.
*
* @param hal Context of the HAL layer
*
* @return if the intr is triggered. 1: triggered, 0: not triggered.
*/
bool dac_dma_hal_get_intr_status(dac_hal_context_t *hal);
/**
* DAC DMA HAL deinitialization
*
* @param hal Context of the HAL layer
*/
void dac_dma_hal_deinit(dac_hal_context_t *hal);
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
void __attribute__((deprecated)) dac_hal_digi_controller_config(const dac_digi_config_t *cfg);
#ifdef __cplusplus
}
#endif

40
components/hal/esp32s2/include/hal/dac_ll.h
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@@ -25,6 +25,9 @@
extern "C" {
#endif
#define DAC_LL_CW_PHASE_0 0x02
#define DAC_LL_CW_PHASE_180 0x03
/*---------------------------------------------------------------
DAC common setting
---------------------------------------------------------------*/
@@ -67,10 +70,10 @@ static inline void dac_ll_power_down(dac_channel_t channel)
*/
static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value)
{
if (channel == DAC_CHANNEL_1) {
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
} else if (channel == DAC_CHANNEL_2) {
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
}
@@ -124,9 +127,9 @@ static inline void dac_ll_cw_generator_disable(void)
*/
static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
{
if (channel == DAC_CHANNEL_1) {
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = enable;
} else if (channel == DAC_CHANNEL_2) {
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = enable;
}
}
@@ -135,11 +138,12 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
* Set frequency of cosine wave generator output.
*
* @note We know that CLK8M is about 8M, but don't know the actual value. so this freq have limited error.
* @param freq_hz CW generator frequency. Range: 130(130Hz) ~ 55000(100KHz).
* @param freq_hz CW generator frequency. Range: >= 130(130Hz)
* @param rtc8m_freq the calibrated RTC 8M clock frequency
*/
static inline void dac_ll_cw_set_freq(uint32_t freq)
static inline void dac_ll_cw_set_freq(uint32_t freq, uint32_t rtc8m_freq)
{
uint32_t sw_freq = freq * 0xFFFF / SOC_CLK_RC_FAST_FREQ_APPROX;
uint32_t sw_freq = (uint32_t)(((float)freq / (float)rtc8m_freq) * 65536);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
}
@@ -151,9 +155,9 @@ static inline void dac_ll_cw_set_freq(uint32_t freq)
*/
static inline void dac_ll_cw_set_scale(dac_channel_t channel, uint32_t scale)
{
if (channel == DAC_CHANNEL_1) {
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_scale1 = scale;
} else if (channel == DAC_CHANNEL_2) {
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_scale2 = scale;
}
}
@@ -162,13 +166,13 @@ static inline void dac_ll_cw_set_scale(dac_channel_t channel, uint32_t scale)
* Set the phase of the cosine wave generator output.
*
* @param channel DAC channel num.
* @param scale Phase value.
* @param phase Phase value. 0: 0x02 180: 0x03.
*/
static inline void dac_ll_cw_set_phase(dac_channel_t channel, uint32_t phase)
{
if (channel == DAC_CHANNEL_1) {
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_inv1 = phase;
} else if (channel == DAC_CHANNEL_2) {
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_inv2 = phase;
}
}
@@ -183,14 +187,14 @@ static inline void dac_ll_cw_set_phase(dac_channel_t channel, uint32_t phase)
*/
static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
{
if (channel == DAC_CHANNEL_1) {
if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) {
offset = 0 - offset;
if (channel == DAC_CHAN_0) {
if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_LL_CW_PHASE_180) {
offset = -offset;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset);
} else if (channel == DAC_CHANNEL_2) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) {
offset = 0 - offset;
} else if (channel == DAC_CHAN_1) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_LL_CW_PHASE_180) {
offset = -offset;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset);
}