dac: update unit-test docs and examples for driver-NG

components/soc/esp32/dac_periph.c

@@ -1,16 +1,8 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "soc/dac_periph.h"
 
@@ -18,6 +10,6 @@
  Bunch of constants for DAC peripheral: GPIO number
 */
 const dac_signal_conn_t dac_periph_signal = {
-    .dac_channel_io_num[0] = DAC_CHANNEL_1_GPIO_NUM,
-    .dac_channel_io_num[1] = DAC_CHANNEL_2_GPIO_NUM,
+    .dac_channel_io_num[0] = DAC_CHAN_0_GPIO_NUM,
+    .dac_channel_io_num[1] = DAC_CHAN_1_GPIO_NUM,
 };

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -251,6 +251,10 @@ config SOC_DAC_RESOLUTION
     int
     default 8
 
+config SOC_DAC_DMA_16BIT_ALIGN
+    bool
+    default y
+
 config SOC_GPIO_PORT
     int
     default 1

components/soc/esp32/include/soc/clk_tree_defs.h

@@ -277,6 +277,37 @@ typedef enum {
     SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
 } soc_periph_sdm_clk_src_t;
 
+////////////////////////////////////////////////////DAC/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of DAC digital controller
+ */
+#define SOC_DAC_DIGI_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL}
+
+/**
+ * @brief DAC digital controller clock source
+ *
+ */
+typedef enum {
+    DAC_CLK_SRC_PLLD2 = SOC_MOD_CLK_PLL_D2,
+    DAC_DIGI_CLK_SRC_APLL = SOC_MOD_CLK_APLL,
+    DAC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2,
+} soc_periph_dac_digi_clk_src_t;
+
+/**
+ * @brief Array initializer for all supported clock sources of DAC cosine wave generator
+ */
+#define SOC_DAC_COSINE_CLKS {DAC_COSINE_CLK_SRC_RTC}
+
+/**
+ * @brief DAC cosine wave generator clock source
+ *
+ */
+typedef enum {
+    DAC_COSINE_CLK_SRC_RTC = SOC_MOD_CLK_RTC_FAST,
+    DAC_COSINE_CLK_SRC_DEFAULT = SOC_MOD_CLK_RTC_FAST,
+} soc_periph_dac_cosine_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32/include/soc/dac_channel.h

@@ -1,24 +1,16 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #ifndef _SOC_DAC_CHANNEL_H
 #define _SOC_DAC_CHANNEL_H
 
-#define DAC_GPIO25_CHANNEL      DAC_CHANNEL_1
-#define DAC_CHANNEL_1_GPIO_NUM  25
+#define DAC_GPIO25_CHANNEL      DAC_CHAN_0
+#define DAC_CHAN_0_GPIO_NUM     25
 
-#define DAC_GPIO26_CHANNEL      DAC_CHANNEL_2
-#define DAC_CHANNEL_2_GPIO_NUM  26
+#define DAC_GPIO26_CHANNEL      DAC_CHAN_1
+#define DAC_CHAN_1_GPIO_NUM     26
 
 #endif

components/soc/esp32/include/soc/soc_caps.h

@@ -148,8 +148,9 @@
 #define SOC_CPU_WATCHPOINT_SIZE         64 // bytes
 
 /*-------------------------- DAC CAPS ----------------------------------------*/
-#define SOC_DAC_PERIPH_NUM      2
-#define SOC_DAC_RESOLUTION      8 // DAC resolution ratio 8 bit
+#define SOC_DAC_PERIPH_NUM              2
+#define SOC_DAC_RESOLUTION              8 // DAC resolution ratio 8 bit
+#define SOC_DAC_DMA_16BIT_ALIGN         1 // The DMA data should left shift 8 bit to be aligned with 16 bit
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32 has 1 GPIO peripheral