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change(esp32c5): update soc files for esp32c5 beta3

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This commit is contained in:
laokaiyao
2023-12-25 15:32:55 +08:00
parent cf43d60c63
commit fcc9293f66
77 changed files with 13318 additions and 9401 deletions
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348
components/hal/esp32c5/include/hal/mmu_ll.h
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@@ -9,7 +9,7 @@
#pragma once
#include "soc/spi_mem_reg.h"
// #include "soc/ext_mem_defs.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#include "hal/efuse_ll.h"
@@ -29,8 +29,7 @@ extern "C" {
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
return (uint32_t)0;
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
}
/**
@@ -45,21 +44,19 @@ static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)target;
// (void)vaddr_type;
// //On ESP32C5, I/D share the same vaddr range
// return SOC_MMU_IBUS_VADDR_BASE | laddr;
return (uint32_t)0;
(void)target;
(void)vaddr_type;
//On ESP32C5, I/D share the same vaddr range
return SOC_MMU_IBUS_VADDR_BASE | laddr;
}
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// unsigned cnt = efuse_ll_get_flash_crypt_cnt();
// // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
// cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
// return (cnt == 1);
return (bool)0;
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
return (cnt == 1);
}
/**
@@ -73,13 +70,12 @@ __attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
// return (page_size_code == 0) ? MMU_PAGE_64KB :
// (page_size_code == 1) ? MMU_PAGE_32KB :
// (page_size_code == 2) ? MMU_PAGE_16KB :
// MMU_PAGE_8KB;
return (mmu_page_size_t)0;
(void)mmu_id;
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE);
return (page_size_code == 0) ? MMU_PAGE_64KB :
(page_size_code == 1) ? MMU_PAGE_32KB :
(page_size_code == 2) ? MMU_PAGE_16KB :
MMU_PAGE_8KB;
}
/**
@@ -91,11 +87,11 @@ __attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 :
// (size == MMU_PAGE_32KB) ? 1 :
// (size == MMU_PAGE_16KB) ? 2 :
// (size == MMU_PAGE_8KB) ? 3 : 0;
// REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 :
(size == MMU_PAGE_32KB) ? 1 :
(size == MMU_PAGE_16KB) ? 2 :
(size == MMU_PAGE_8KB) ? 3 : 0;
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE, reg_val);
}
/**
@@ -113,11 +109,10 @@ __attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// (void)type;
// uint32_t vaddr_end = vaddr_start + len - 1;
// return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
return (bool)0;
(void)mmu_id;
(void)type;
uint32_t vaddr_end = vaddr_start + len - 1;
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
}
/**
@@ -133,11 +128,10 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
// (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
// ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
return (bool)0;
(void)mmu_id;
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
}
/**
@@ -153,27 +147,26 @@ __attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
return (uint32_t)0;
(void)mmu_id;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
}
/**
@@ -190,28 +183,27 @@ __attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// (void)target;
// mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// return paddr >> shift_code;
return (uint32_t)0;
(void)mmu_id;
(void)target;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return paddr >> shift_code;
}
/**
@@ -225,15 +217,16 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// (void)target;
// uint32_t mmu_raw_value;
// if (mmu_ll_cache_encryption_enabled()) {
// mmu_val |= SOC_MMU_SENSITIVE;
// }
// // mmu_raw_value = mmu_val | SOC_MMU_VALID;
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
(void)mmu_id;
(void)target;
uint32_t mmu_raw_value;
if (mmu_ll_cache_encryption_enabled()) {
mmu_val |= SOC_MMU_SENSITIVE;
}
mmu_raw_value = mmu_val | SOC_MMU_VALID;
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
}
/**
@@ -246,20 +239,19 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// uint32_t mmu_raw_value;
// uint32_t ret;
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
// if (mmu_ll_cache_encryption_enabled()) {
// mmu_raw_value &= ~SOC_MMU_SENSITIVE;
// }
// if (!(mmu_raw_value & SOC_MMU_VALID)) {
// return 0;
// }
// ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
// return ret;
return (uint32_t)0;
(void)mmu_id;
uint32_t mmu_raw_value;
uint32_t ret;
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
if (mmu_ll_cache_encryption_enabled()) {
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
}
if (!(mmu_raw_value & SOC_MMU_VALID)) {
return 0;
}
ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
return ret;
}
/**
@@ -271,9 +263,9 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
(void)mmu_id;
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
}
/**
@@ -285,9 +277,9 @@ __attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
// mmu_ll_set_entry_invalid(mmu_id, i);
// }
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i);
}
}
/**
@@ -301,11 +293,11 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
// // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
return (bool)0;
(void)mmu_id;
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
}
/**
@@ -319,9 +311,8 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// return MMU_TARGET_FLASH0;
return (mmu_target_t)0;
(void)mmu_id;
return MMU_TARGET_FLASH0;
}
/**
@@ -335,29 +326,30 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
// // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
return (uint32_t)0;
(void)mmu_id;
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
}
/**
@@ -374,19 +366,19 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
// if (mmu_ll_check_entry_valid(mmu_id, i)) {
// if (mmu_ll_get_entry_target(mmu_id, i) == target) {
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
// if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
// return i;
// }
// }
// }
// }
// // return -1;
return (int)0;
(void)mmu_id;
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
if (mmu_ll_check_entry_valid(mmu_id, i)) {
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
return i;
}
}
}
}
return -1;
}
/**
@@ -399,35 +391,35 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// // switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// uint32_t laddr = entry_id << shift_code;
// // /**
// * For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
// * Here we just pass MMU_TARGET_FLASH0 to get vaddr
// */
// return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
return (uint32_t)0;
(void)mmu_id;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
uint32_t laddr = entry_id << shift_code;
/**
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
*/
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
}
#ifdef __cplusplus
return (uint32_t)0;
}
#endif