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change(esp32c5): update soc files for esp32c5 beta3

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This commit is contained in:
laokaiyao
2023-12-25 15:32:55 +08:00
parent cf43d60c63
commit fcc9293f66
77 changed files with 13318 additions and 9401 deletions
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4
components/soc/esp32c5/include/soc/soc.h
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@@ -26,7 +26,7 @@
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_TWAI_BASE(i) ((i) == 0 ? DR_REG_TWAI0_BASE : DR_REG_TWAI1_BASE) // TWAI0 and TWAI1
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000)
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
@@ -153,7 +153,7 @@
* should be defined statically!
*/
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_LOW 0x41000000
#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8))
#define SOC_DROM_LOW SOC_IROM_LOW
#define SOC_DROM_HIGH SOC_IROM_HIGH