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modify csv & generate
update efuse_reg.h & efuse_struct.h & references in rst file
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@@ -141,12 +141,12 @@ extern "C" {
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#define EFUSE_DIS_ICACHE_M (BIT(8))
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#define EFUSE_DIS_ICACHE_V 0x1
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#define EFUSE_DIS_ICACHE_S 8
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/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */
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/*description: Set this bit to disable boot from RTC RAM.*/
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#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7))
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#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7))
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#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1
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#define EFUSE_DIS_RTC_RAM_BOOT_S 7
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/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED5 (BIT(7))
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#define EFUSE_RPT4_RESERVED5_M (BIT(7))
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#define EFUSE_RPT4_RESERVED5_V 0x1
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#define EFUSE_RPT4_RESERVED5_S 7
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/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
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/*description: Set this bit to disable reading from BlOCK4-10.*/
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#define EFUSE_RD_DIS 0x0000007F
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@@ -516,12 +516,12 @@ extern "C" {
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#define EFUSE_DIS_ICACHE_M (BIT(8))
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#define EFUSE_DIS_ICACHE_V 0x1
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#define EFUSE_DIS_ICACHE_S 8
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/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */
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/*description: The value of DIS_RTC_RAM_BOOT.*/
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#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7))
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#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7))
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#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1
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#define EFUSE_DIS_RTC_RAM_BOOT_S 7
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/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED5 (BIT(7))
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#define EFUSE_RPT4_RESERVED5_M (BIT(7))
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#define EFUSE_RPT4_RESERVED5_V 0x1
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#define EFUSE_RPT4_RESERVED5_S 7
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/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
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/*description: The value of RD_DIS.*/
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#define EFUSE_RD_DIS 0x0000007F
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@@ -1486,12 +1486,12 @@ extern "C" {
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#define EFUSE_DIS_ICACHE_ERR_M (BIT(8))
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#define EFUSE_DIS_ICACHE_ERR_V 0x1
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#define EFUSE_DIS_ICACHE_ERR_S 8
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/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
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/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/
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#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7))
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#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7))
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#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1
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#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7
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/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
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/*description: Reserved..*/
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#define EFUSE_RPT4_RESERVED5_ERR (BIT(7))
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#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7))
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#define EFUSE_RPT4_RESERVED5_ERR_V 0x1
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#define EFUSE_RPT4_RESERVED5_ERR_S 7
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/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
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/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/
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#define EFUSE_RD_DIS_ERR 0x0000007F
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@@ -22,7 +22,7 @@ typedef volatile struct efuse_dev_s {
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union {
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struct {
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uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/
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uint32_t dis_rtc_ram_boot: 1; /*Set this bit to disable boot from RTC RAM.*/
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uint32_t rpt4_reserved5: 1; /*Reserved*/
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uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/
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uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/
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uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/
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@@ -106,7 +106,7 @@ typedef volatile struct efuse_dev_s {
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union {
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struct {
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uint32_t rd_dis: 7; /*The value of RD_DIS.*/
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uint32_t dis_rtc_ram_boot: 1; /*The value of DIS_RTC_RAM_BOOT.*/
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uint32_t rpt4_reserved5: 1; /*Reserved*/
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uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/
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uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/
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uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/
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@@ -274,7 +274,7 @@ typedef volatile struct efuse_dev_s {
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union {
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struct {
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uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/
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uint32_t dis_rtc_ram_boot_err: 1; /*If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/
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uint32_t rpt4_reserved5_err: 1; /*Reserved.*/
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uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/
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uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/
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uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/
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