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update efuse_reg.h & efuse_struct.h & references in rst file
This commit is contained in:
wuzhenghui
2021-09-17 10:42:04 +08:00
committed by bot
parent 625bd4f767
commit fd5a63f31e
11 changed files with 45 additions and 80 deletions
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36
components/soc/esp32s3/include/soc/efuse_reg.h
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@@ -142,12 +142,12 @@ extern "C" {
#define EFUSE_DIS_ICACHE_M (BIT(8))
#define EFUSE_DIS_ICACHE_V 0x1
#define EFUSE_DIS_ICACHE_S 8
/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to disable boot from RTC RAM.*/
#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1
#define EFUSE_DIS_RTC_RAM_BOOT_S 7
/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Reserved */
#define EFUSE_RPT4_RESERVED5 (BIT(7))
#define EFUSE_RPT4_RESERVED5_M (BIT(7))
#define EFUSE_RPT4_RESERVED5_V 0x1
#define EFUSE_RPT4_RESERVED5_S 7
/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
/*description: Set this bit to disable reading from BlOCK4-10.*/
#define EFUSE_RD_DIS 0x0000007F
@@ -571,12 +571,12 @@ extern "C" {
#define EFUSE_DIS_ICACHE_M (BIT(8))
#define EFUSE_DIS_ICACHE_V 0x1
#define EFUSE_DIS_ICACHE_S 8
/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The value of DIS_RTC_RAM_BOOT.*/
#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1
#define EFUSE_DIS_RTC_RAM_BOOT_S 7
/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Reserved */
#define EFUSE_RPT4_RESERVED5 (BIT(7))
#define EFUSE_RPT4_RESERVED5_M (BIT(7))
#define EFUSE_RPT4_RESERVED5_V 0x1
#define EFUSE_RPT4_RESERVED5_S 7
/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
/*description: The value of RD_DIS.*/
#define EFUSE_RD_DIS 0x0000007F
@@ -1583,12 +1583,12 @@ extern "C" {
#define EFUSE_DIS_ICACHE_ERR_M (BIT(8))
#define EFUSE_DIS_ICACHE_ERR_V 0x1
#define EFUSE_DIS_ICACHE_ERR_S 8
/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/
#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1
#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7
/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Reserved..*/
#define EFUSE_RPT4_RESERVED5_ERR (BIT(7))
#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7))
#define EFUSE_RPT4_RESERVED5_ERR_V 0x1
#define EFUSE_RPT4_RESERVED5_ERR_S 7
/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/
#define EFUSE_RD_DIS_ERR 0x0000007F