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modify csv & generate

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update efuse_reg.h & efuse_struct.h & references in rst file
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wuzhenghui
2021-09-17 10:42:04 +08:00
committed by bot
parent 625bd4f767
commit fd5a63f31e
11 changed files with 45 additions and 80 deletions
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1
docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst
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@@ -8,7 +8,6 @@
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Config fuses:
DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0)
DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0)
DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)
DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0)

1
docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst
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@@ -27,7 +27,6 @@
ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001)
Config fuses:
DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0)
DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0)
DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0)
DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)