alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-10-11 15:21:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

refactor(cache): abstract cache rom API in cache_ll.h

Browse Source
This commit is contained in:
gaoxu
2023-08-07 15:20:00 +08:00
committed by Gao Xu
parent db4308888d
commit fd759d65b0
9 changed files with 1331 additions and 172 deletions
Download Patch File Download Diff File Expand all files Collapse all files

379
components/hal/esp32s2/include/hal/cache_ll.h
View File

@@ -13,6 +13,7 @@
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32s2/rom/cache.h"
#ifdef __cplusplus
extern "C" {
@@ -22,30 +23,384 @@ extern "C" {
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
#define CACHE_LL_L1_DCACHE_AUTOLOAD (1<<0)
/**
* @brief Get the status of cache if it is enabled or not
* @brief Check if ICache auto preload is enabled or not
*
* @param cache_id cache ID (when l1 cache is per core)
* @param type see `cache_type_t`
* @return enabled or not
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_l1_is_icache_autoload_enabled(void)
{
bool enabled = false;
if (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_AUTOLOAD_ENA)) {
enabled = true;
}
return enabled;
}
/**
* @brief Check if DCache auto preload is enabled or not
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_l1_is_cache_enabled(uint32_t cache_id, cache_type_t type)
static inline bool cache_ll_l1_is_dcache_autoload_enabled(void)
{
bool enabled = false;
if (REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_AUTOLOAD_ENA)) {
enabled = true;
}
return enabled;
}
/**
* @brief Check if ICache or DCache auto preload is enabled or not
*
* @param type see `cache_type_t`
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_is_cache_autoload_enabled(cache_type_t type)
{
bool enabled = false;
switch (type)
{
case CACHE_TYPE_INSTRUCTION:
enabled = cache_ll_l1_is_icache_autoload_enabled();
break;
case CACHE_TYPE_DATA:
enabled = cache_ll_l1_is_dcache_autoload_enabled();
break;
default: //CACHE_TYPE_ALL
enabled = cache_ll_l1_is_icache_autoload_enabled() && cache_ll_l1_is_dcache_autoload_enabled();
break;
}
return enabled;
}
/**
* @brief Disable ICache
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_icache(void)
{
Cache_Disable_ICache();
}
/**
* @brief Disable DCache
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_dcache(void)
{
Cache_Disable_DCache();
}
/**
* @brief Disable ICache or DCache or both
*
* @param type see `cache_type_t`
*/
__attribute__((always_inline))
static inline void cache_ll_disable_cache(cache_type_t type)
{
switch (type)
{
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_disable_icache();
break;
case CACHE_TYPE_DATA:
cache_ll_l1_disable_dcache();
break;
default: //CACHE_TYPE_ALL
cache_ll_l1_disable_icache();
cache_ll_l1_disable_dcache();
break;
}
}
/**
* @brief Enable ICache
*
* @param inst_autoload_en ICache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_enable_icache(bool inst_autoload_en)
{
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
* @brief Enable DCache
*
* @param data_autoload_en DCache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_enable_dcache(bool data_autoload_en)
{
Cache_Enable_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
}
/**
* @brief Enable ICache or DCache or both
*
* @param type see `cache_type_t`
*
* @param data_autoload_en Dcache auto preload enabled
*
* @param inst_autoload_en Icache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_enable_cache(cache_type_t type, bool inst_autoload_en, bool data_autoload_en)
{
switch (type)
{
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_enable_icache(inst_autoload_en);
break;
case CACHE_TYPE_DATA:
cache_ll_l1_enable_dcache(data_autoload_en);
break;
default: //CACHE_TYPE_ALL
cache_ll_l1_enable_icache(inst_autoload_en);
cache_ll_l1_enable_dcache(data_autoload_en);
break;
}
}
/**
* @brief Suspend ICache
*/
__attribute__((always_inline))
static inline void cache_ll_l1_suspend_icache(void)
{
Cache_Suspend_ICache();
}
/**
* @brief Suspend DCache
*/
__attribute__((always_inline))
static inline void cache_ll_l1_suspend_dcache(void)
{
Cache_Suspend_DCache();
}
/**
* @brief Suspend ICache or DCache or both
*
* @param type see `cache_type_t`
*/
__attribute__((always_inline))
static inline void cache_ll_suspend_cache(cache_type_t type)
{
switch (type)
{
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_suspend_icache();
break;
case CACHE_TYPE_DATA:
cache_ll_l1_suspend_dcache();
break;
default: //CACHE_TYPE_ALL
cache_ll_l1_suspend_icache();
cache_ll_l1_suspend_dcache();
break;
}
}
/**
* @brief Resume ICache
*
* @param inst_autoload_en ICache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_resume_icache(bool inst_autoload_en)
{
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
* @brief Resume DCache
*
* @param data_autoload_en DCache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_resume_dcache(bool data_autoload_en)
{
Cache_Resume_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
}
/**
* @brief Resume ICache or DCache or both
*
* @param type see `cache_type_t`
*
* @param data_autoload_en Dcache auto preload enabled
*
* @param inst_autoload_en Icache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_resume_cache(cache_type_t type, bool inst_autoload_en, bool data_autoload_en)
{
switch (type)
{
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_resume_icache(inst_autoload_en);
break;
case CACHE_TYPE_DATA:
cache_ll_l1_resume_dcache(data_autoload_en);
break;
default: //CACHE_TYPE_ALL
cache_ll_l1_resume_icache(inst_autoload_en);
cache_ll_l1_resume_dcache(data_autoload_en);
break;
}
}
/**
* @brief Check if ICache is enabled or not
*
* @param cache_id cache ID (when l1 cache is per core)
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id){
HAL_ASSERT(cache_id == 0);
bool enabled;
enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE);
return enabled;
}
/**
* @brief Check if DCache is enabled or not
*
* @param cache_id cache ID (when l1 cache is per core)
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_l1_is_dcache_enabled(uint32_t cache_id)
{
HAL_ASSERT(cache_id == 0);
bool enabled;
if (type == CACHE_TYPE_INSTRUCTION) {
enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE);
} else if (type == CACHE_TYPE_DATA) {
enabled = REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE);
} else {
enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE);
enabled = enabled && REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE);
enabled = REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE);
return enabled;
}
/**
* @brief Check if ICache or DCache or both is enabled or not
*
* @param type see `cache_type_t`
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
{
bool enabled = false;
switch (type)
{
case CACHE_TYPE_DATA:
enabled = cache_ll_l1_is_dcache_enabled(0);
break;
case CACHE_TYPE_INSTRUCTION:
enabled = cache_ll_l1_is_icache_enabled(0);
break;
default: //CACHE_TYPE_ALL
enabled = cache_ll_l1_is_dcache_enabled(0) && cache_ll_l1_is_icache_enabled(0);
break;
}
return enabled;
}
/**
* @brief Invalidate cache supported addr
*
* Invalidate a Cache item for either ICache or DCache.
*
* @param vaddr Start address of the region to be invalidated
* @param size Size of the region to be invalidated
*/
__attribute__((always_inline))
static inline void cache_ll_invalidate_addr(uint32_t vaddr, uint32_t size)
{
Cache_Invalidate_Addr(vaddr, size);
}
/**
* @brief Writeback cache supported addr
*
* Writeback the DCache item to external memory
*
* @param vaddr Start address of the region to writeback
* @param size Size of the region to writeback
*/
__attribute__((always_inline))
static inline void cache_ll_writeback_addr(uint32_t vaddr, uint32_t size)
{
Cache_WriteBack_Addr(vaddr, size);
}
/**
* @brief Get ICache line size, in bytes
*
* @return ICache line size, in bytes
*/
__attribute__((always_inline))
static inline uint32_t cache_ll_l1_icache_get_line_size(void)
{
uint32_t size = 0;
size = Cache_Get_ICache_Line_Size();
return size;
}
/**
* @brief Get DCache line size, in bytes
*
* @return DCache line size, in bytes
*/
__attribute__((always_inline))
static inline uint32_t cache_ll_l1_dcache_get_line_size(void)
{
uint32_t size = 0;
size = Cache_Get_DCache_Line_Size();
return size;
}
/**
* @brief Get ICache or DCache line size, in bytes
*
* @param type see `cache_type_t`
*
* @return ICache/DCache line size, in bytes
*/
__attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(cache_type_t type)
{
uint32_t size = 0;
switch (type)
{
case CACHE_TYPE_INSTRUCTION:
size = cache_ll_l1_icache_get_line_size();
break;
case CACHE_TYPE_DATA:
size = cache_ll_l1_dcache_get_line_size();
break;
default: //CACHE_TYPE_ALL
HAL_ASSERT(false);
break;
}
return size;
}
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*