diff --git a/components/esp_hal_pmu/esp32h4/include/hal/pmu_ll.h b/components/esp_hal_pmu/esp32h4/include/hal/pmu_ll.h index d29735d240..8e5a68a902 100644 --- a/components/esp_hal_pmu/esp32h4/include/hal/pmu_ll.h +++ b/components/esp_hal_pmu/esp32h4/include/hal/pmu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_hw_support/port/esp32h4/pmu_init.c b/components/esp_hw_support/port/esp32h4/pmu_init.c index 2948d43797..1a1db472e2 100644 --- a/components/esp_hw_support/port/esp32h4/pmu_init.c +++ b/components/esp_hw_support/port/esp32h4/pmu_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,15 +11,15 @@ #include "esp_attr.h" #include "soc/soc.h" #include "soc/pmu_struct.h" +#include "soc/pmu_reg.h" #include "hal/pmu_hal.h" #include "pmu_param.h" #include "esp_private/esp_pmu.h" -#include "soc/regi2c_dcdc.h" -#include "soc/regi2c_ulp.h" -#include "soc/lp_aon_reg.h" -#include "soc/rtc.h" #include "regi2c_ctrl.h" +#include "hal/regi2c_ctrl_ll.h" #include "esp_rom_sys.h" +#include "soc/regi2c_ulp.h" +#include "hal/lp_aon_ll.h" static __attribute__((unused)) const char *TAG = "pmu_init"; @@ -121,6 +121,21 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys /* set dcdc ccm mode software enable */ pmu_ll_set_dcdc_ccm_sw_en(ctx->hal->dev, true); + +#if CONFIG_ESP32H4_SELECTS_REV_MP + /* set ble bandgap ocode */ + uint32_t ulp_ocode = 0; +#if !CONFIG_IDF_ENV_FPGA + bool ulp_force_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE); + if (ulp_force_flag) { + ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_EXT_CODE); + } else { + ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_OCODE); + } +#endif + REG_SET_FIELD(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_OCODE, ulp_ocode); + SET_PERI_REG_MASK(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_FORCE_OCODE); +#endif } void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_system_param_t *param) @@ -233,38 +248,19 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx) } } -uint32_t get_ulp_ocode() -{ - uint32_t ulp_ocode = 0; -#if !CONFIG_IDF_ENV_FPGA - bool ulp_force_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE); - if (ulp_force_flag) { - ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_EXT_CODE); - } else { - ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_OCODE); - } -#endif - return ulp_ocode; -} - void pmu_init(void) { + /* Peripheral reg i2c power up */ + regi2c_ctrl_ll_i2c_sar_periph_enable(); + regi2c_ctrl_ll_i2c_rftx_periph_enable(); + regi2c_ctrl_ll_i2c_rfrx_periph_enable(); + + //Initialize hp and lp systems pmu_hp_system_init_default(PMU_instance()); pmu_lp_system_init_default(PMU_instance()); pmu_power_domain_force_default(PMU_instance()); -#if !CONFIG_IDF_ENV_FPGA - REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_DREG0, 24); - REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_PCUR_LIMIT0, 4); - REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_DREG0, 24); - REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_PCUR_LIMIT0, 2); - REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_XPD_TRX, 0); -#endif - - // close rfpll to decrease mslp_cur - REG_SET_FIELD(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL, 1); - REG_SET_FIELD(PMU_RF_PWC_REG, PMU_XPD_RFPLL, 0); #if !CONFIG_IDF_ENV_FPGA // TODO: IDF-12313 @@ -272,12 +268,4 @@ void pmu_init(void) // esp_ocode_calib_init(); // } #endif - - uint32_t ulp_ocode = get_ulp_ocode(); - REG_SET_FIELD(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_OCODE, ulp_ocode); - SET_PERI_REG_MASK(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_FORCE_OCODE); - - //For dcdc ldo mode when VDD is low than about a certion value, eg 2.6v - CLEAR_PERI_REG_MASK(LP_AON_DATE_REG, LP_AON_DREG_LDO_HW); - REG_SET_FIELD(LP_AON_DATE_REG, LP_AON_DREG_LDO_SW, 15); } diff --git a/components/esp_hw_support/port/esp32h4/pmu_sleep.c b/components/esp_hw_support/port/esp32h4/pmu_sleep.c index 73a35ae8a4..24c0070865 100644 --- a/components/esp_hw_support/port/esp32h4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h4/pmu_sleep.c @@ -148,11 +148,11 @@ const pmu_sleep_config_t* pmu_sleep_config_default( config->digital = digital_default; pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags); - analog_default.hp_sys.analog.dbias = PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT; + analog_default.hp_sys.analog.drv_b = PMU_HP_DRVB_LIGHTSLEEP; analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_slp_lp_dbias(); if (!(sleep_flags & PMU_SLEEP_PD_XTAL)){ analog_default.hp_sys.analog.xpd_trx = PMU_XPD_TRX_SLEEP_ON; - analog_default.hp_sys.analog.dbias = get_act_hp_drvb(); + analog_default.hp_sys.analog.drv_b = get_act_hp_drvb(); analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON; analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; @@ -160,7 +160,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default( analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias(); } else if (!(sleep_flags & PMU_SLEEP_PD_RC_FAST)) { - analog_default.hp_sys.analog.dbias = get_act_hp_drvb(); + analog_default.hp_sys.analog.drv_b = get_act_hp_drvb(); analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias(); } config->analog = analog_default; @@ -173,6 +173,7 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi pmu_ll_hp_set_dig_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.dig_power.val); pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val); pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal); + pmu_ll_hp_set_xtalx2_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtalx2); if (dslp) { pmu_ll_hp_set_memory_power_on_mask(ctx->hal->dev, 0); @@ -186,6 +187,7 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val); pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val); pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal); + pmu_ll_lp_set_xtalx2_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtalx2); } static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig) @@ -200,8 +202,8 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur); pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep); pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); - pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); + pmu_ll_hp_set_trx_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd_trx); pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep); diff --git a/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h index cd56292903..caaac44eb4 100644 --- a/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h4/private_include/pmu_param.h @@ -159,7 +159,8 @@ typedef union { uint32_t pd_osc : 1; }; struct { - uint32_t reserved2 : 31; + uint32_t reserved2 : 30; + uint32_t xpd_xtalx2 : 1; uint32_t xpd_xtal : 1; }; uint32_t val; @@ -329,7 +330,8 @@ typedef struct { }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .dig_power = { \ - .vdd_io_mode = 3, \ + /* TODO: PM-638 */\ + .vdd_io_mode = 0, \ .bod_source_sel = 0, \ .vddbat_mode = 0, \ .peri_pd_en = ((sleep_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0,\ @@ -342,6 +344,7 @@ typedef struct { .xpd_fosc = ((sleep_flags) & PMU_SLEEP_PD_RC_FAST) ? 0 : 1 \ }, \ .xtal = { \ + .xpd_xtalx2 = 0, \ .xpd_xtal = ((sleep_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \ } \ } \ @@ -373,7 +376,7 @@ typedef struct { .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 1, \ .dig_reg_dsfmos = 4, \ - .dcm_vset = 23, \ + .dcm_vset = 20, \ .dcm_mode = 3, \ .discnnt_dig_rtc = 0, \ .xpd_trx = 0, \ @@ -391,7 +394,7 @@ typedef struct { .dcdc_clear_rdy = 0, \ .dig_reg_dpcur_bias = 1, \ .dig_reg_dsfmos = 4, \ - .dcm_vset = 0, \ + .dcm_vset = 20, \ .dcm_mode = 3, \ .discnnt_dig_rtc = 0, \ .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ @@ -525,15 +528,15 @@ typedef struct pmu_sleep_machine_constant { .min_slp_time_us = 450, \ .clock_domain_sync_time_us = 150, \ .system_dfs_up_work_time_us = 124, \ - .analog_wait_time_us = 2200, \ + .analog_wait_time_us = 190, \ .isolate_wait_time_us = 1, \ .reset_wait_time_us = 1, \ .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2, \ .regdma_s2m_work_time_us = 172, \ - .regdma_s2a_work_time_us = 280, \ + .regdma_s2a_work_time_us = 365, \ .regdma_m2a_work_time_us = 278, \ - .regdma_a2s_work_time_us = 220, \ + .regdma_a2s_work_time_us = 265, \ .regdma_rf_on_work_time_us = 70, \ .regdma_rf_off_work_time_us = 23, \ .xtal_wait_stable_time_us = 160, \ diff --git a/components/hal/esp32h4/include/hal/lp_aon_ll.h b/components/hal/esp32h4/include/hal/lp_aon_ll.h index ffb2c67986..5a00458d3d 100644 --- a/components/hal/esp32h4/include/hal/lp_aon_ll.h +++ b/components/hal/esp32h4/include/hal/lp_aon_ll.h @@ -106,6 +106,12 @@ static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr) HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr); } +static inline void lp_aon_ll_set_ldo_sw(uint32_t value) +{ + CLEAR_PERI_REG_MASK(LP_AON_DATE_REG, LP_AON_DREG_LDO_HW); + REG_SET_FIELD(LP_AON_DATE_REG, LP_AON_DREG_LDO_SW, value); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h index 319c8bfde8..c241530213 100644 --- a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h @@ -113,6 +113,38 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void) CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); } +/** + * @brief Enable the RF TX I2C internal bus power domain + */ +static inline void regi2c_ctrl_ll_i2c_rftx_periph_enable(void) +{ + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFTX_I2C); +} + +/** + * @brief Disable the RF TX I2C internal bus power domain + */ +static inline void regi2c_ctrl_ll_i2c_rftx_periph_disable(void) +{ + CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFTX_I2C); +} + +/** + * @brief Enable the RF RX I2C internal bus power domain + */ +static inline void regi2c_ctrl_ll_i2c_rfrx_periph_enable(void) +{ + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFRX_I2C); +} + +/** + * @brief Disable the RF RX I2C internal bus power domain + */ +static inline void regi2c_ctrl_ll_i2c_rfrx_periph_disable(void) +{ + CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFRX_I2C); +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h4/register/soc/lp_aon_reg.h b/components/soc/esp32h4/register/soc/lp_aon_reg.h index 3db0abe9f2..73eda6dbe2 100644 --- a/components/soc/esp32h4/register/soc/lp_aon_reg.h +++ b/components/soc/esp32h4/register/soc/lp_aon_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */