mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-27 02:16:51 +00:00
rmt: split TX and RX in LL driver
Split TX and RX function in LL driver. Channel number is encoded in driver layer. Added channel signal list in periph.c
This commit is contained in:
morris
@@ -25,19 +25,8 @@ extern "C" {
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#define RMT_LL_HW_BASE (&RMT)
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#define RMT_LL_MEM_BASE (&RMTMEM)
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#define RMT_LL_TX_CHAN_NUM (4)
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#define RMT_LL_TX_CHAN_MASK (0x0F)
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#define RMT_LL_RX_CHAN_MASK (0xF0)
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static inline void rmt_ll_set_sclk(rmt_dev_t *dev, uint32_t source, uint32_t div_num, uint32_t div_frac_a, uint32_t div_frac_b)
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{
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dev->sys_conf.sclk_active = 0;
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dev->sys_conf.sclk_sel = source;
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dev->sys_conf.sclk_div_num = div_num;
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dev->sys_conf.sclk_div_a = div_frac_a;
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dev->sys_conf.sclk_div_b = div_frac_b;
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dev->sys_conf.sclk_active = 1;
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}
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// Note: TX and RX channel number are all index from zero in the LL driver
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// i.e. tx_channel belongs to [0,3], and rx_channel belongs to [0,3]
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static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
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{
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@@ -45,46 +34,6 @@ static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
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dev->sys_conf.mem_clk_force_on = enable; // memory clock gating
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}
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static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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dev->ref_cnt_rst.val |= (1 << channel);
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dev->ref_cnt_rst.val &= ~(1 << channel);
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}
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static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_conf[channel].mem_rd_rst = 1;
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dev->tx_conf[channel].mem_rd_rst = 0;
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dev->tx_conf[channel].apb_mem_rst = 1;
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dev->tx_conf[channel].apb_mem_rst = 0;
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}
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static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_wr_rst = 1;
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_wr_rst = 0;
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.apb_mem_rst = 1;
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.apb_mem_rst = 0;
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}
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static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_conf[channel].conf_update = 1;
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dev->tx_conf[channel].tx_start = 1;
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}
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static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_conf[channel].tx_stop = 1;
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dev->tx_conf[channel].conf_update = 1;
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}
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static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_en = enable;
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.conf_update = 1;
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}
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static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
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{
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dev->sys_conf.mem_force_pu = !enable;
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@@ -99,67 +48,139 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev)
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return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu);
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}
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static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
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{
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if(channel < RMT_LL_TX_CHAN_NUM) {
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dev->tx_conf[channel].mem_size = block_num;
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} else {
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.mem_size = block_num;
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}
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}
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static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
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{
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return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_conf[channel].mem_size) : (dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.mem_size);
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}
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static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
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{
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if(channel < RMT_LL_TX_CHAN_NUM) {
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dev->tx_conf[channel].div_cnt = div;
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} else {
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.div_cnt = div;
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}
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}
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static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_conf[channel].div_cnt) : (dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.div_cnt);
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}
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static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->tx_conf[channel].mem_tx_wrap_en = enable;
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}
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static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
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{
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dev->sys_conf.fifo_mask = enable;
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}
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static inline void rmt_ll_set_rx_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b)
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{
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.idle_thres = thres;
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// Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b)
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dev->sys_conf.sclk_active = 0;
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dev->sys_conf.sclk_sel = src;
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dev->sys_conf.sclk_div_num = div_num;
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dev->sys_conf.sclk_div_a = div_a;
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dev->sys_conf.sclk_div_b = div_b;
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dev->sys_conf.sclk_active = 1;
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}
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static inline uint32_t rmt_ll_get_rx_idle_thres(rmt_dev_t *dev, uint32_t channel)
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static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.idle_thres;
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return dev->sys_conf.sclk_sel;
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}
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static inline void rmt_ll_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
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static inline void rmt_ll_tx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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if (channel >= RMT_LL_TX_CHAN_NUM) {
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_owner = owner;
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}
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dev->ref_cnt_rst.val |= (1 << channel);
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dev->ref_cnt_rst.val &= ~(1 << channel);
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}
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static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
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static inline void rmt_ll_rx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_owner;
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dev->ref_cnt_rst.val |= (1 << (channel + 4));
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dev->ref_cnt_rst.val &= ~(1 << (channel + 4));
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}
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static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
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static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_conf[channel].mem_rd_rst = 1;
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dev->tx_conf[channel].mem_rd_rst = 0;
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dev->tx_conf[channel].apb_mem_rst = 1;
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dev->tx_conf[channel].apb_mem_rst = 0;
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}
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static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
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{
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dev->rx_conf[channel].conf1.mem_wr_rst = 1;
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dev->rx_conf[channel].conf1.mem_wr_rst = 0;
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dev->rx_conf[channel].conf1.apb_mem_rst = 1;
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dev->rx_conf[channel].conf1.apb_mem_rst = 0;
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}
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static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_conf[channel].conf_update = 1;
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dev->tx_conf[channel].tx_start = 1;
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}
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static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_conf[channel].tx_stop = 1;
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dev->tx_conf[channel].conf_update = 1;
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}
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static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->rx_conf[channel].conf1.rx_en = enable;
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dev->rx_conf[channel].conf1.conf_update = 1;
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}
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static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
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{
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dev->tx_conf[channel].mem_size = block_num;
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}
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static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
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{
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dev->rx_conf[channel].conf0.mem_size = block_num;
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}
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static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->tx_conf[channel].mem_size;
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}
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static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->rx_conf[channel].conf0.mem_size;
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}
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static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
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{
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dev->tx_conf[channel].div_cnt = div;
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}
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static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
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{
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dev->rx_conf[channel].conf0.div_cnt = div;
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}
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static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->tx_conf[channel].div_cnt;
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}
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static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->rx_conf[channel].conf0.div_cnt;
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}
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static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->tx_conf[channel].mem_tx_wrap_en = enable;
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}
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static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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{
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dev->rx_conf[channel].conf0.idle_thres = thres;
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}
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static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->rx_conf[channel].conf0.idle_thres;
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}
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static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
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{
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dev->rx_conf[channel].conf1.mem_owner = owner;
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}
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static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->rx_conf[channel].conf1.mem_owner;
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}
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static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->tx_conf[channel].tx_conti_mode = enable;
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}
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@@ -169,62 +190,49 @@ static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel)
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return dev->tx_conf[channel].tx_conti_mode;
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}
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static inline void rmt_ll_set_tx_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
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static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
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{
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dev->tx_lim[channel].tx_loop_num = count;
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}
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static inline void rmt_ll_reset_tx_loop(rmt_dev_t *dev, uint32_t channel)
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static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_lim[channel].loop_count_reset = 1;
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dev->tx_lim[channel].loop_count_reset = 0;
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}
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static inline void rmt_ll_enable_tx_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable)
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static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->tx_lim[channel].tx_loop_cnt_en = enable;
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}
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static inline void rmt_ll_enable_tx_sync(rmt_dev_t *dev, bool enable)
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static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable)
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{
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dev->tx_sim.en = enable;
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}
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static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel)
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static inline void rmt_ll_tx_add_channel_to_group(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_sim.val |= 1 << channel;
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}
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static inline uint32_t rmt_ll_remove_channel_from_group(rmt_dev_t *dev, uint32_t channel)
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static inline uint32_t rmt_ll_tx_remove_channel_from_group(rmt_dev_t *dev, uint32_t channel)
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{
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dev->tx_sim.val &= ~(1 << channel);
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return dev->tx_sim.val & RMT_LL_TX_CHAN_MASK;
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return dev->tx_sim.val & 0x0F;
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}
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static inline void rmt_ll_enable_rx_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
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static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_filter_en = enable;
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dev->rx_conf[channel].conf1.rx_filter_en = enable;
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}
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static inline void rmt_ll_set_rx_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
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{
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dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_filter_thres = thres;
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dev->rx_conf[channel].conf1.rx_filter_thres = thres;
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}
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static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src)
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{
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dev->sys_conf.sclk_sel = src;
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dev->sys_conf.sclk_div_num = 0;
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dev->sys_conf.sclk_div_a = 0;
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dev->sys_conf.sclk_div_b = 0;
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}
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static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->sys_conf.sclk_sel;
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}
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static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
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static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->tx_conf[channel].idle_out_en = enable;
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}
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@@ -234,173 +242,175 @@ static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
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return dev->tx_conf[channel].idle_out_en;
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}
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static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
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static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
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{
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dev->tx_conf[channel].idle_out_lv = level;
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}
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static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel)
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static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->tx_conf[channel].idle_out_lv;
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}
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static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
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static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel)
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{
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return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_status[channel].val) : (dev->rx_status[channel - RMT_LL_TX_CHAN_NUM].val);
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return dev->rx_status[channel].val;
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}
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static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
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static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel)
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{
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return dev->tx_status[channel].val;
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}
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static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
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{
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dev->tx_lim[channel].limit = limit;
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}
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static inline void rmt_ll_set_rx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
|
||||
static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
|
||||
{
|
||||
dev->rx_lim[channel - RMT_LL_TX_CHAN_NUM].rx_lim = limit;
|
||||
dev->rx_lim[channel].rx_lim = limit;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_rx_limit(rmt_dev_t *dev, uint32_t channel)
|
||||
static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->rx_lim[channel - RMT_LL_TX_CHAN_NUM].rx_lim;
|
||||
return dev->rx_lim[channel].rx_lim;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (BIT(0) << (channel));
|
||||
dev->int_ena.val |= (1 << channel);
|
||||
} else {
|
||||
dev->int_ena.val &= ~(BIT(0) << (channel));
|
||||
dev->int_ena.val &= ~(1 << channel);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (1 << (channel + 4));
|
||||
} else {
|
||||
dev->int_ena.val &= ~(1 << (channel + 4));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
dev->int_ena.val |= (1 << (channel + 16));
|
||||
} else {
|
||||
dev->int_ena.val &= ~(BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
dev->int_ena.val &= ~(1 << (channel + 16));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if(channel < RMT_LL_TX_CHAN_NUM) {
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (BIT(4) << (channel));
|
||||
} else {
|
||||
dev->int_ena.val &= ~(BIT(4) << (channel));
|
||||
}
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (1 << (channel + 20));
|
||||
} else {
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
} else {
|
||||
dev->int_ena.val &= ~(BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
}
|
||||
dev->int_ena.val &= ~(1 << (channel + 20));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (BIT(8) << (channel));
|
||||
dev->int_ena.val |= (1 << (channel + 8));
|
||||
} else {
|
||||
dev->int_ena.val &= ~(BIT(8) << (channel));
|
||||
dev->int_ena.val &= ~(1 << (channel + 8));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (BIT(12) << (channel));
|
||||
dev->int_ena.val |= (1 << (channel + 12));
|
||||
} else {
|
||||
dev->int_ena.val &= ~(BIT(12) << (channel));
|
||||
dev->int_ena.val &= ~(1 << (channel + 12));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= (BIT(24) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
dev->int_ena.val |= (1 << (channel + 24));
|
||||
} else {
|
||||
dev->int_ena.val &= ~(BIT(24) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
dev->int_ena.val &= ~(1 << (channel + 24));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->int_clr.val = (BIT(0) << (channel));
|
||||
dev->int_clr.val = (1 << (channel));
|
||||
}
|
||||
|
||||
static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->int_clr.val = (BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
dev->int_clr.val = (1 << (channel + 16));
|
||||
}
|
||||
|
||||
static inline void rmt_ll_clear_err_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
if(channel < RMT_LL_TX_CHAN_NUM) {
|
||||
dev->int_clr.val = (BIT(4) << (channel));
|
||||
} else {
|
||||
dev->int_clr.val = (BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
|
||||
}
|
||||
dev->int_clr.val = (1 << (channel + 4));
|
||||
}
|
||||
|
||||
static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->int_clr.val = (1 << (channel + 20));
|
||||
}
|
||||
|
||||
static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->int_clr.val = (BIT(8) << (channel));
|
||||
dev->int_clr.val = (1 << (channel + 8));
|
||||
}
|
||||
|
||||
static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->int_clr.val = (BIT(12) << (channel));
|
||||
dev->int_clr.val = (1 << (channel + 12));
|
||||
}
|
||||
|
||||
static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->int_clr.val = (BIT(24) << (channel -RMT_LL_TX_CHAN_NUM));
|
||||
dev->int_clr.val = (1 << (channel + 24));
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & RMT_LL_TX_CHAN_MASK;
|
||||
return dev->int_st.val & 0x0F;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return (dev->int_st.val >> 12) & RMT_LL_RX_CHAN_MASK;
|
||||
return (dev->int_st.val >> 16) & 0x0F;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return (dev->int_st.val >> 4) & RMT_LL_TX_CHAN_MASK;
|
||||
return (dev->int_st.val >> 4) & 0x0F;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return (dev->int_st.val >> 16) & RMT_LL_RX_CHAN_MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_err_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return ((dev->int_st.val >> 4) & RMT_LL_TX_CHAN_MASK) | ((dev->int_st.val >> 16) & RMT_LL_RX_CHAN_MASK);
|
||||
return (dev->int_st.val >> 20) & 0x0F;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return (dev->int_st.val >> 8) & RMT_LL_TX_CHAN_MASK;
|
||||
return (dev->int_st.val >> 8) & 0x0F;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return (dev->int_st.val >> 20) & RMT_LL_RX_CHAN_MASK;
|
||||
return (dev->int_st.val >> 24) & 0x0F;
|
||||
}
|
||||
|
||||
static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
|
||||
{
|
||||
return (dev->int_st.val >> 12) & RMT_LL_TX_CHAN_MASK;
|
||||
return (dev->int_st.val >> 12) & 0x0F;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
|
||||
static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
|
||||
{
|
||||
// In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
|
||||
// We take care of the "read-modify-write" procedure by ourselves.
|
||||
@@ -410,44 +420,44 @@ static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
|
||||
dev->tx_carrier[channel].val = reg.val;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
|
||||
static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
|
||||
{
|
||||
typeof(dev->rx_carrier[0]) reg;
|
||||
reg.high_thres = high_ticks;
|
||||
reg.low_thres = low_ticks;
|
||||
dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].val = reg.val;
|
||||
dev->rx_carrier[channel].val = reg.val;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
|
||||
static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks )
|
||||
{
|
||||
if (channel < RMT_LL_TX_CHAN_NUM) {
|
||||
*high_ticks = dev->tx_carrier[channel].high;
|
||||
*low_ticks = dev->tx_carrier[channel].low;
|
||||
} else {
|
||||
*high_ticks = dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].high_thres;
|
||||
*low_ticks = dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].low_thres;
|
||||
}
|
||||
*high_ticks = dev->tx_carrier[channel].high;
|
||||
*low_ticks = dev->tx_carrier[channel].low;
|
||||
}
|
||||
|
||||
// This function has different meaning for TX and RX
|
||||
// TX: enable to modulate carrier
|
||||
// RX: enable to demodulate carrier
|
||||
static inline void rmt_ll_enable_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
|
||||
{
|
||||
if (channel < RMT_LL_TX_CHAN_NUM) {
|
||||
dev->tx_conf[channel].carrier_en = enable;
|
||||
} else {
|
||||
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.carrier_en = enable;
|
||||
}
|
||||
*high_ticks = dev->rx_carrier[channel].high_thres;
|
||||
*low_ticks = dev->rx_carrier[channel].low_thres;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
|
||||
static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
if (channel < RMT_LL_TX_CHAN_NUM) {
|
||||
dev->tx_conf[channel].carrier_out_lv = level;
|
||||
} else {
|
||||
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.carrier_out_lv = level;
|
||||
}
|
||||
dev->tx_conf[channel].carrier_en = enable;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->rx_conf[channel].conf0.carrier_en = enable;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
|
||||
{
|
||||
dev->tx_conf[channel].carrier_out_lv = level;
|
||||
}
|
||||
|
||||
static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
|
||||
{
|
||||
dev->rx_conf[channel].conf0.carrier_out_lv = level;
|
||||
}
|
||||
|
||||
// set true, enable carrier in all RMT state (idle, reading, sending)
|
||||
@@ -457,37 +467,22 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan
|
||||
dev->tx_conf[channel].carrier_eff_en = !enable;
|
||||
}
|
||||
|
||||
//Writes items to the specified TX channel memory with the given offset and writen length.
|
||||
//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS)
|
||||
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
|
||||
{
|
||||
length = (off + length) > SOC_RMT_CHANNEL_MEM_WORDS ? (SOC_RMT_CHANNEL_MEM_WORDS - off) : length;
|
||||
for (uint32_t i = 0; i < length; i++) {
|
||||
mem->chan[channel].data32[i + off].val = data[i].val;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_enable_rx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_rx_wrap_en = enable;
|
||||
}
|
||||
|
||||
static inline void rmt_write_fifo(rmt_dev_t *dev, uint32_t channel, const rmt_item32_t *data, uint32_t length)
|
||||
{
|
||||
for (uint32_t i = 0; i < length; i++) {
|
||||
dev->data_ch[channel] = data[i].val;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void rmt_ll_config_update(rmt_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
if(channel < RMT_LL_TX_CHAN_NUM) {
|
||||
dev->tx_conf[channel].conf_update = 1;
|
||||
} else {
|
||||
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.conf_update = 1;
|
||||
}
|
||||
dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable;
|
||||
}
|
||||
|
||||
/************************************************************************************************
|
||||
* Following Low Level APIs only used for backward compatible, will be deprecated in the future!
|
||||
* Following Low Level APIs only used for backward compatible, will be deprecated in the IDF v5.0
|
||||
***********************************************************************************************/
|
||||
|
||||
static inline void rmt_ll_set_intr_enable_mask(uint32_t mask)
|
||||
|
||||
Reference in New Issue
Block a user