140 Commits

Author SHA1 Message Date
Xiao Xufeng
438e07b30e refactor: Remove idf_test component
Split the idf_performance.h and target ver, which hold the performance
thresholds, into the headers of each testing.

In the past pytest also parse the common header to get the thresholds.
Now the logic is also removed. Performance thresholds are supposed to be
in the pytest scripts.
2026-01-01 02:26:42 +08:00
Erhan Kurubas
7ffc500eb4 fix(xtensa): Fix clang assembler errors in STRUCT_AFIELD_A macro 2025-12-17 22:12:34 +01:00
Alexey Lapshin
31810ae993 feat(esp_libc): make picolibc default libc 2025-12-03 13:31:42 +07:00
Erhan Kurubas
083999290e fix(espcoredump): prevent double exception during int_wdt panic with custom stack 2025-11-20 11:14:42 +01:00
Erhan Kurubas
79cda70029 change(app_trace): move sysview to component registry 2025-11-10 15:55:41 +08:00
Roland Dobai
a0b589c147 Merge branch 'feat/cmakev2' into 'master'
feat(cmakev2): introduce cmake-based build system v2

See merge request espressif/esp-idf!42691
2025-11-04 02:53:36 +01:00
Erhan Kurubas
1dac8685db feat(tracing): add new component for tracing 2025-10-30 12:15:35 +01:00
Frantisek Hrbata
427c5ba8df fix(xtensa/cmake): do not include project_include.cmake if the architecture is not xtensa
In cmakev2, the project_include.cmake files for every component are
included. This means that even when working with RISC-V, the
project_include.cmake file for Xtensa is still included. Ensure that the
architecture is verified, and exit if it is not Xtensa.

Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
2025-10-30 17:17:49 +08:00
Peter Dragun
e3198fff3c feat: Update esptool to v5 2025-09-30 15:28:55 +02:00
Ivan Grokhotkov
47f695a930 change(xtensa): use add_prebuilt_library to add blobs 2025-07-17 09:33:21 +08:00
Nebojsa Cvetkovic
d0ceef20f4 refactor(xtensa): Rename specreg.h register macros
This commit renames all registers in xtensa/specreg.h to by adding the
prefix XT_REG_. This is done to avoid naming collisions with similar
variable names. A new register file, viz., xt_specreg.h is created. The
previous names are still available to use but have been deprecated.

Closes https://github.com/espressif/esp-idf/issues/12723
Merges https://github.com/espressif/esp-idf/pull/16040
2025-06-17 15:37:33 +02:00
Erhan Kurubas
cead328c1c feat(apptrace): Store CRC16 checksum value of exposed block in the perfmon reg 2025-05-15 12:17:58 +02:00
Alexey Lapshin
244c369cd8 fix(xtensa): fix confusing backtrace when PC is invalid
Before this change _invalid_pc_placeholder pointed to address of _init
function from crti.o
This made GDB input a bit confusing:

  0x40080400 in _init ()
  (gdb) bt
  #0  0x40080400 in _init ()
  #1  0x400e519a in test_instr_fetch_prohibited () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_panic.c:271
  #2  0x400d89a7 in app_main () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_app_main.c:116
  #3  0x400e5f22 in main_task (args=0x0) at /home/alex/git/esp-idf/components/freertos/app_startup.c:208
  #4  0x400895a8 in vPortTaskWrapper (pxCode=0x400e5eb0 <main_task>, pvParameters=0x0) at /home/alex/git/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:139

After the change GDB prints output that contains a hint:

  _invalid_pc_placeholder () at /home/alex/git/esp-idf/components/xtensa/xtensa_vectors.S:2235
  2235	    UNREACHABLE_INSTRUCTION_CHECK_PREVIOUS_FRAMES
  (gdb) bt
  #0  _invalid_pc_placeholder () at /home/alex/git/esp-idf/components/xtensa/xtensa_vectors.S:2235
  #1  0x400e519e in test_instr_fetch_prohibited () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_panic.c:271
  #2  0x400d89ab in app_main () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_app_main.c:116
  #3  0x400e5f26 in main_task (args=0x0) at /home/alex/git/esp-idf/components/freertos/app_startup.c:208
  #4  0x400895a8 in vPortTaskWrapper (pxCode=0x400e5eb4 <main_task>, pvParameters=0x0) at /home/alex/git/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:139
2024-12-02 21:36:00 +07:00
Erhan Kurubas
8e532baf1e docs(jtag): update OpenOCD related sections 2024-09-30 08:48:33 +02:00
Alexey Gerenkov
57f61d2311 feat(tools): Update Clang version to esp-17.0.1_20240419 2024-05-03 16:55:13 +03:00
Omar Chebib
5cdf145f55 refactor(riscv): refactor crosscore interrupt 2024-01-18 16:27:36 +08:00
Erhan Kurubas
ca0b112669 feat(license): Dual-license source files built by OpenOCD stub flasher 2024-01-15 23:45:23 +01:00
Darian Leung
8c2949a97e change(xtensa): Deprecate ".../xtensa_timer.h" include path
This commit deprecates the "freertos/xtensa_timer.h" and "xtensa/xtensa_timer.h"
include paths. Users should use "xtensa_timer.h" instead.

- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_timer.h"
- Add warning to compatibility header
2023-11-30 21:58:52 +08:00
Darian Leung
a5d5ee7445 change(xtensa): Deprecate ".../xtensa_context.h" include path
This commit deprecates the "freertos/xtensa_context.h" and "xtensa/xtensa_context.h"
include paths. Users should use "xtensa_context.h" instead.

- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Add warning to compatibility header
2023-11-30 21:58:52 +08:00
Darian Leung
2204c8e137 change(xtensa): Deprecate ".../xtensa_api.h" include path
This commit deprecates the "freertos/xtensa_api.h" and "xtensa/xtensa_api.h"
include paths. Users should use "xtensa_api.h" instead.

- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Replaced some calls with "esp_cpu_..." equivalents
- Add warning to compatibility header
2023-11-30 21:58:52 +08:00
Alexey Lapshin
33d9fd629d fix(xtensa): fix registers curruption on context switch
a6, a7 registers may be corrupted on multicore ESP chips while FreeRTOS
Kernel SMP context switch
2023-10-09 12:13:02 +04:00
Omar Chebib
b03c8912c7 Xtensa: fix a bug that altered CPU registers in FPU exception handlers
* Fixes https://github.com/espressif/esp-idf/issues/11690
2023-07-04 02:45:56 +00:00
Frantisek Hrbata
b3998f0f0c tools: strip trailing whitespaces/newline from dump_machine
In components/xtensa/project_include.cmake ${CMAKE_C_COMPILER} -dumpmachine
is called, but the output has newline.

Before
---8<--
-- Compiler supported targets: xtensa-esp32s3-elf

-- App "blink" version: 1.2.3
---8<--

After
---8<--
-- Compiler supported targets: xtensa-esp32s3-elf
-- App "blink" version: 1.2.3
---8<--

Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
2023-05-30 13:35:10 +02:00
Jakob Hasse
0a3cfce671 Merge branch 'contrib/github_pr_10895' into 'master'
Fix possible conversion errors by using __builtin_ffsll (GitHub PR)

Closes IDFGH-9541

See merge request espressif/esp-idf!23429
2023-05-04 10:41:46 +08:00
Ivan Grokhotkov
9d82d6bf7f xtensa: don't print debug messages to stderr
By default, CMake message() commands prints to stderr.
IDEs like Eclipse show stderr output in red, which looks as if this is
some kind of error.

Use message(STATUS) instead.
2023-04-25 12:59:41 +02:00
Darian Leung
6587e75251 xtensa: Add bare metal port stub functions for G0 build test
This commit adds "bare metal stubs" xtensa_rtos.h glue layer to mimic a bare
metal OS port. The bare metal stubs don't access any components outside of the
G0 group.
2023-04-18 15:51:38 +08:00
Darian Leung
b2c074bb70 xtensa: Move Xtensa RTOS porting layer files to xtensa component
When porting an RTOS to the Xtensa architecture, there are a few files that
are common to all Xtensa RTOS ports. These files form the Xtensa RTOS porting
layer (e.g., "xtensa_vectors.S", "xtensa_context.S"). An Xtensa RTOS port is
expected to provide an RTOS specific "xtensa_rtos.h" header to interface with
the Xtensa RTOS porting layer.

Previously, the Xtensa RTOS porting layer files were placed in the FreeRTOS
component. This commit does the following:

1. Moves the Xtensa RTOS porting layer files from the `freertos` component to
the `xtensa` component. The following files were moved:

    - xtensa_asm_utils.h
    - xtensa_context.S
    - xtensa_loadstore_handler.S
    - xtensa_vectors.S

2. Refactored xtensa component include paths to separate Xtensa RTOS porting
layer headers.

- Xtensa HAL headers included via `#include <xtensa/...h>`
- Xtensa RTOS porting layer headers included via `#include <...h>`

Note: The xtensa files in the Amazon SMP FreeRTOS port are not moved/deleted in
this commit to ensure the moved files retain a clean diff history.
2023-04-18 15:28:05 +08:00
term_est
14724d1cb9 Fix possible conversion errors by using __builtin_ffsll instead of __builtin_ffs
Signed-off-by: term_est <62337595+term-est@users.noreply.github.com>
2023-03-03 11:21:07 +03:00
Omar Chebib
1ff8a68c21 Merge branch 'bugfix/support_coredump_stack_xtensa' into 'master'
coredump: custom core dump stack is now supported on Xtensa targets

See merge request espressif/esp-idf!21335
2022-12-19 18:02:15 +08:00
Andrei Safronov
9d257054c8 xtensa: remove asm struct expressions in header files 2022-12-05 22:00:07 +03:00
Omar Chebib
301cb74890 coredump: custom core dump stack is now supported on Xtensa targets 2022-12-02 12:01:19 +08:00
Alexey Gerenkov
47c2c13de5 build: Adds support for universal Clang toolchain 2022-11-23 13:25:16 +03:00
Ivan Grokhotkov
a97686f607 xtensa: fix swapped breakpoint and watchpoint numbers 2022-07-25 09:43:10 +02:00
Omar Chebib
8fae0f0753 G0: Support Xtensa targets for G0-only compilation
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
2022-06-20 11:34:20 +00:00
Darian Leung
434287fc8b freertos: Xtensa FreeRTOS saves threadptr in solicited stack frame
The Xtensa FreeRTOS port does not save the threadptr register when
doing a voluntary yield. This can result in a crash when multiple
tasks used the threadptr register and call "taskYIELD()".

This commit adds the threadptr register to the solicited stack frame.
2022-06-15 20:20:41 +08:00
Darian Leung
a8a3756b38 hal: Route CPU and Interrupt Controller HAL/LL to esp_cpu calls
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:

- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead

Also updated soc_hal.h as follows:

- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.

This commit also updates the XCHAL_ERRATUM_572 workaround by

- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
2022-06-14 14:40:03 +08:00
Darian Leung
61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
2022-06-14 14:30:58 +08:00
Anton Maklakov
d1db4d0c1b system: add missing header 2022-05-30 12:43:23 +07:00
Marius Vikhammer
9362434c47 build-system: add property for architecture (riscv/xtensa)
riscv/xtensa is now a common component.
2022-05-20 09:00:32 +08:00
Erhan Kurubas
ad078c5153 semihosting: drop absolute path support 2022-05-05 09:12:42 +00:00
Erhan Kurubas
0fc0254734 semihosting: version 2 2022-05-05 09:12:42 +00:00
Marius Vikhammer
e543e97c7b system: fix SET_STACK macro crashing in windowoverflow8 exception
If a windowoverflow8 happened after changing the SP, the exception handler would look for
the extra save area by looking at the previous frame's SP. This SP would be a garbage value
and could cause the windowoverflow exception to write to invalid memory ares.
2022-03-04 15:25:52 +08:00
Darian Leung
1c60d6a895 freertos: Add SPDX license identifiers and update xtensa port files
This commit does the following:

- Adds SPDX license identifiers to FreeRTOS sources. Remove those FreeRTOS sources from
  the copyright ignore list.
- Update xtensa port files to match FreeRTOS v10.4.3. Added SPDX license identifiers
  to the port files.
- Fixed some improperly licensed files
- Removed portbenchmark.h from RISC-V port
2022-02-03 17:08:14 +08:00
Ivan Grokhotkov
aeed91b589 xtensa: fix semihosting arguments potentially begin optimized out
The compiler was not informed that the assembly block should be
treated as a memory barrier and could optimize out the initialization
of local arrays which could be used as semihosting arguments.
This resulted in garbage values being passed as semihosting call
arguments.

Additionally this commit changes the approach for placing values into
specific register. Instead of clobbers, local register variables are
used. This results in simpler generated code, since the compiler is
able to place values directly into the registers used for semihosting
arguments, avoiding additional moves.
2022-01-20 19:48:05 +01:00
laokaiyao
cf049e15ed esp8684: rename target to esp32c2 2022-01-19 11:08:57 +08:00
Ivan Grokhotkov
876f4d6a1c vfs: add support for semihosting on ESP32-C3 2022-01-14 17:29:03 +01:00
morris
113cbb88a6 hw_support: remove deprecated header files 2022-01-04 14:16:17 +08:00
Sudeep Mohanty
e22b4007d3 esp_hw_support: Removed deprecated CPU util functions
The following files were deleted:
- components/esp_hw_support/include/soc/cpu.h
- components/soc/esp32s3/include/soc/cpu.h

The following functions are deprecated:
- get_sp()

The following functions declared in soc/cpu.h are now moved to esp_cpu.h:
- esp_cpu_configure_region_protection()

The following functions declared in soc/cpu.h are now moved to components/xtensa/include/esp_cpu_utils.h:
- esp_cpu_process_stack_pc()

All files with soc/cpu.h inclusion are updated to include esp_cpu.h instead.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2021-12-28 16:58:37 +05:30
Roland Dobai
2b9c81cbdc xtensa: Pass the test with latest gdb 2021-11-22 18:17:36 +01:00
Roland Dobai
1c22f1e15e xtensa: Revert back Makefile for trax test
Revert back the regression of 766aa57084
2021-11-22 18:02:08 +01:00