12 Commits

Author	SHA1	Message	Date
baohongde	1f152b5146	Waits for all previously fetched WSR and XSR instructions to be performed before interpreting the register fields of the next ... instruction delete logs about livelock	2021-01-06 14:21:54 +08:00
baohongde	a3188d7fd9	Fix live lock in bt isr immediately	2020-07-20 17:10:04 +08:00
Li Shuai	c69c066641	Fix live lock int bt isr using cod multicore debug	2020-07-20 17:10:04 +08:00
Li Shuai	61b646aa8a	optimize the live lock soft solution process	2020-07-20 17:09:49 +08:00
Li Shuai	76717f72d6	add debug code for wdt reset	2020-07-20 17:09:49 +08:00
Li Shuai	fa0348b512	Fixed interrupt watchdog error caused by live lock	2020-07-20 17:09:48 +08:00
Li Shuai	a80cf2dc69	Fix interrupt watchdog caused by livelock	2020-07-20 17:09:48 +08:00
baohongde	a172605af4	components/bt: using high level interrupt in lc	2020-04-17 23:16:59 +08:00
Konstantin Kondrashov	2e9904556f	esp32: Dis interrupts up to 5 lvl for DPORT ... Disable interrupts for both DPORT workarounds up to 5 lvl. Closes: https://esp32.com/viewtopic.php?f=2&t=10981&sid=d125cec233070ed4d2c5410bf5d3d74a Closes: IDF-728	2019-08-21 09:48:16 +00:00
Ivan Grokhotkov	834c056234	xtensa: remove unused header files	2018-05-31 02:21:36 +00:00
Ivan Grokhotkov	6b61c6d39f	esp32: exclude DPORT-related code in single core mode	2017-09-22 12:07:05 +08:00
Jeroen Domburg	d3290479b2	Merge panic and dport high level interrupt code to both use int level 4	2017-07-07 12:51:33 +08:00