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Commit Graph

135 Commits

Author SHA1 Message Date
Laukik Hase
f2b0f256ab fix(esp_rom): Patch the esp_rom_delay_us API to use U-mode cycle CSR 2025-07-25 09:54:42 +05:30
armando
bcf04e356b resolve comments, to squash 2025-07-10 06:24:32 +00:00
armando
dfb0662de2 feat(esp32p4): support eco5 on fpga 2025-07-10 06:24:32 +00:00
laokaiyao
db85cd02be refactor(esp32c61): bus_monitor backward compatible refactor 2025-04-08 22:50:04 +08:00
Chen Jichang
6c4271d4bb feat(esp32h4): disable unsupported build 2025-03-28 14:41:29 +08:00
Omar Chebib
0bc169e735 fix(freertos): optimize HWLP context switch by disabling it when unused 2025-03-13 11:11:24 +08:00
Omar Chebib
c26879d29e fix(freertos): workaround a hardware bug related to HWLP coprocessor 
This commit manually sets the HWLP context to dirty when a Task that needs it is scheduled it.
 2025-03-13 11:11:24 +08:00
Chen Jichang
30f2578e75 fix(esp32h4): fix g0 component build 2025-03-04 16:17:18 +08:00
Chen Jichang
62700fa36f feat(esp32h4): add soc register header files (stage2_3) 
add soc headers made by hand
 2025-02-24 12:20:27 +08:00
Jiang Jiang Jian
44a27d3113 Merge branch 'fix/disable_wfe_feature_for_e906_chips' into 'master' 
change(esp_hw_support): disable CPU wait-for-event mode on cpu start

See merge request espressif/esp-idf!36388
 2025-02-11 11:30:29 +08:00
Laukik Hase
c4eec756f3 refactor(esp_tee): Revised the secure service ID numbering scheme 
Also:
- Split the secure service table into two parts: one DRAM-resident and the
  other DROM-resident. The former holds the services invoked when the cache is
  disabled or suspended while the latter holds rest of the services.
 2025-01-23 12:39:19 +05:30
wuzhenghui
121f56ef6d change(esp_hw_support): disable CPU wait-for-event mode on cpu start 2025-01-14 21:34:44 +08:00
Laukik Hase
e51d2c1da3 feat(esp_tee): Support for ESP-TEE - riscv component 2024-12-02 12:20:04 +05:30
Mahavir Jain
2a6be654cd Merge branch 'ci/enable_memprot_tests_for_esp32c61' into 'master' 
Clear PMA entries before usage and enable tests for ESP32-C61

Closes IDF-10932

See merge request espressif/esp-idf!33438
 2024-09-20 21:32:18 +08:00
Alexey Gerenkov
9ca231e76e change(build): Use integrated assembler with Clang for RISCV chips 2024-09-18 21:40:39 +03:00
harshal.patil
7667d9ebbe fix(cpu_region_protect): Reset PMA entries before using them 
- ROM uses some PMA entries so we clear such PMA entries before using them in ESP-IDF
 2024-09-18 10:25:18 +05:30
Liu Xiao Yu
52175a6548 Merge branch 'refactor/supplement_plic_intr_rv_util_apis' into 'master' 
refactor(intr): add plic and intc interrupt rv util apis

See merge request espressif/esp-idf!33244
 2024-09-12 15:28:24 +08:00
Xiaoyu Liu
8a608da2b0 refactor(intr): add plic and intc interrupt rv util apis 
refactor(intr): remove the extra instructions in plic and intc
 2024-09-11 18:26:07 +08:00
Armando
17fc026c48 fix(pma): fixed pma 15 occupied by rom on c5 issue 2024-09-10 11:12:02 +08:00
Marius Vikhammer
6e51c0525d fix(wdt): changed register dump on non panic task WDT to be more descriptive 
Closes https://github.com/espressif/esp-idf/issues/14400
 2024-08-22 10:48:26 +08:00
Armando
893c04702f feat(riscv): added api to disable branch predictor 2024-08-14 14:34:34 +08:00
Omar Chebib
f06b235709 fix(riscv): fix a that affected mintstatus CSR value in the CLIC 2024-07-26 13:56:40 +08:00
Armando
c880f697da feat(panic): supported more cache error cactch 2024-07-11 15:26:13 +08:00
laokaiyao
21f870ecd5 remove(c5beta3): remove c5 beta3 system files 2024-06-17 12:02:15 +08:00
Marius Vikhammer
eb24a57728 feat(intr): basic interrupt/freertos support for C61 2024-06-12 09:25:47 +08:00
Omar Chebib
82668dd3fe fix(riscv): make HWLP feature use direct saving of lazy saving 2024-05-21 17:27:46 +08:00
Omar Chebib
55acc5e5e7 feat(riscv): add support for PIE coprocessor and HWLP feature 
FreeRTOS tasks may now freely use the PIE coprocessor and HWLP feature.
Just like the FPU, usiing these coprocessors result in the task being pinned
to the core it is currently running on.
 2024-05-20 10:47:58 +08:00
Marius Vikhammer
4b4f4c200a fix(interrupt): fixed interrupt thresholds not working on C5 2024-05-14 10:56:22 +08:00
Alexey Lapshin
6f2de1fb23 fix(system): esp32p4: fix mepc when load/store failure occurred 2024-04-18 19:49:19 +04:00
Omar Chebib
f6e935e013 fix(esp32c5): add CLIC interrupt controller support for the ESP32-C5 2024-04-16 10:38:14 +08:00
Mahavir Jain
166fa7acac fix: minor warning related to missing parenthesis 2024-04-14 21:16:34 +05:30
Konstantin Kondrashov
06c28f0ee9 feat(hal): Adds hal funcs for cpu.c 2024-04-11 13:07:04 +03:00
Jiang Jiang Jian
8fcf5270a2 Merge branch 'fix/exception_vectors' into 'master' 
fix: mark .exception_vectors* as executable and allocatable

Closes IDF-9554

See merge request espressif/esp-idf!29782
 2024-04-02 00:08:07 +08:00
Marius Vikhammer
be839733ed fix(interrupt): fixed exit critical section on P4/C5 
When adjusting the interrupt level treshold on P4/C6 during a critical section exit
it would take a few cycles before this is taken into account by the CPU.

This meant that under some circumstances, e.g. 02, we could do
yield()->vPortExitCritical()->vPortEnterCritical()
without getting rescheduled.
This causes issues for freertos as it assumes the task will not continue into the
vPortEnterCritical before the scheduler has schedulded it again.

This meant that e.g. xTaskNotifyWait would yield, but then immeditaly continue as if
it was already notified.
 2024-03-24 13:13:42 +08:00
Kevin (Lao Kaiyao)
4cd30f9b8f Merge branch 'feature/esp32c5_mp_bringup' into 'master' 
feat(esp32c5): bringup esp32c5 mp (Stage 7/7: hello world)

See merge request espressif/esp-idf!29093
 2024-03-22 11:18:52 +08:00
Alexey Lapshin
13b55386bf feat(system): esp32p4: support hw stack guard 2024-03-21 14:30:21 +04:00
laokaiyao
c9d6a11d1d feat(esp32c5mp): support to run hello world on esp32c5 mp 2024-03-21 16:18:03 +08:00
Frantisek Hrbata
359af26736 fix: mark .exception_vectors* as executable and allocatable 
It seems gcc is not producing debug information for sections which
are not properly marked as "ax", resulting in missing debug info
for _vector_table, _interrupt_handler and _panic_handler. This can be
verified e.g. with

readelf --debug=info ./build/esp-idf/riscv/CMakeFiles/__idf_riscv.dir/vectors.S.obj
readelf -SW ./build/esp-idf/riscv/CMakeFiles/__idf_riscv.dir/vectors.S.obj

for hello_world example on esp32c3 target. Mark the .exception_vectors.text and
.exception_vectors_table.text sections as writable and allocatable so the debug
info sections are generated.

Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
 2024-03-21 08:53:09 +01:00
Wan Lei
a7355d3aba Merge branch 'feat/c6lite_c61_g0_component_s4' into 'master' 
feat(esp32c61): add G0 component (hal, riscv) support (stage 4/8)

See merge request espressif/esp-idf!29551
 2024-03-20 10:09:42 +08:00
wanlei
37dfd8fb52 feat(esp32c61): add G0 component support 2024-03-18 14:28:27 +08:00
wuzhenghui
03e5e4970d refactor(esp_hw_support): split pd_cpu retention initialization by target 2024-03-15 18:13:24 +08:00
Sudeep Mohanty
459ff8348f fix(riscv): Added RISC-V functions to set interrupt threshold for CLIC targets 
This commit added the RISC-V utility functions to set the interrupt
threshold for CLIC targets by using direct register value writes.
This makes the functions more efficient during run-time.
This is done to improve the critical section enter and exit performance on esp32p4.
 2024-02-28 08:51:37 +01:00
Omar Chebib
2217854092 fix(riscv): Remove the memory barrier when changing interrupt threshold 2024-02-20 12:19:08 +08:00
Darian Leung
f50d83413e refactor(tools): Tidy up core component files copyright ignore 
Some files that should have their copyrights checked are still placed on the
copyright ignore list.

- These entries have been tidied up
- Copyrights of those files have been updated.
 2024-01-22 18:07:35 +08:00
Omar Chebib
cdde05335e Merge branch 'refactor/riscv_interrupt' into 'master' 
refactor(riscv): Refactor crosscore interrupts and core interrupt code

Closes IDF-5720, DOC-5177, and IDF-7899

See merge request espressif/esp-idf!27845
 2024-01-19 10:51:04 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
Omar Chebib
c7e63078b7 fix(riscv): adjust TCBs lowest stack address when the FPU is used 2024-01-18 13:06:29 +08:00
Sudeep Mohanty
d4ca7c246e fix(freertos): Fixed incorrect int level restoration on esp32p4 
This commit fixes a bug where in the portENABLE_INTERRUPTS() macro
incorrectly restored the interrupt level to 1 (non-CLIC controller).
 2024-01-05 11:00:56 +01:00
Marius Vikhammer
9f1d001849 Merge branch 'feat/cache_error_c6_h2' into 'master' 
fix(panic): fixed cache error being reported as illegal instruction

Closes IDF-6398, IDF-5657, IDF-7015, and IDF-6733

See merge request espressif/esp-idf!27430
 2023-12-21 10:32:06 +08:00
laokaiyao
2b44d62e43 feat(esp32c5): support esp32c5 g0 components 2023-12-08 15:12:24 +08:00