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1d866dc4a0fb98266e5f2a20c4920d34abfaaf10
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6 Commits

Author SHA1 Message Date
Angus Gratton
420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00
Ivan Grokhotkov
d742bc85a5 gdbstub: fix CONFIG_ESP_CONSOLE_UART_NUM option name 2019-07-18 09:33:40 +02:00
Ivan Grokhotkov
7d21ece78b gdbstub: move to a separate component, support multiple targets 2019-07-17 16:01:03 +02:00
Ivan Grokhotkov
66e0b2f9df gdbstub: move to a separate component, support multiple targets 2019-07-02 11:06:25 +02:00