12 Commits

Author	SHA1	Message	Date
wanckl	fb2f5cc1da	feat(driver_spi): c5 eco2 support master rx timing sample phase	2025-04-16 21:24:38 +08:00
laokaiyao	0abc755342	feat(rom): update rom for c5 eco2 ... Breaking: Starting from this commit, ESP-IDF can only support ESP32-C5 v1.0 (ECO2)	2025-04-16 11:01:36 +08:00
wanckl	ef7406257a	feat(driver_spi): spi master support sleep retention(recovery)	2024-10-24 12:47:32 +08:00
laokaiyao	82f4add36d	refactor(soc): sort esp32c5 soc headers	2024-10-11 16:32:52 +08:00
wanckl	473f39c31f	fix(driver_spi): move macro GPIO_MATRIX_DELAY_NS out from soc.h	2024-09-03 13:55:00 +08:00
harshal.patil	980ac9bcf5	fix(soc): Fix ESP32-C5's rom mask high and subsystem high memory addresses	2024-06-25 11:39:22 +05:30
laokaiyao	717a2ccf15	remove(c5beta3): remove c5 beta3 soc files	2024-06-17 12:01:57 +08:00
laokaiyao	319e30ac38	refactor(esp32c5): change beta3 path in soc	2024-03-01 10:16:14 +08:00
Mahavir Jain	9ecd2fd7e3	fix(soc): change debug addr range to CPU subsystem range ... For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same address range is part of CPU Subsystem range which contains debug mode specific code and interrupt config registers (CLINT, PLIC etc.). For now the PMP entry is provided with RWX permission for both machine and user mode but we can save this entry and allow the access to only machine mode for this range. For P4/C5 case, this PMP entry can have RW permission as the debug mode specific code is not present in this memory range.	2024-01-22 13:34:32 +08:00
Song Ruo Jing	7f2b85b82b	feat(clk): add basic clock support for esp32p4 ... - Support CPU frequency 360MHz - Support SOC ROOT clock source switch - Support LP SLOW clock source switch - Support clock calibration	2023-12-29 00:37:26 +08:00
laokaiyao	fcc9293f66	change(esp32c5): update soc files for esp32c5 beta3	2023-12-28 10:23:15 +08:00
laokaiyao	2b44d62e43	feat(esp32c5): support esp32c5 g0 components	2023-12-08 15:12:24 +08:00