Darian Leung
1fabfd005b
soc: Fix SOC_IROM_MASK_HIGH address
...
The high address limit IROM on the esp32s2 is incorrect, thus
causing backtrace printing to think valid function PCs are invalid.
2021-01-25 14:54:25 +08:00
Angus Gratton
420aef1ffe
Updates for riscv support
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* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
longer signed/unsigned int).
Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
Renz Bagaporo
79887fdc6c
soc: descriptive part occupy whole component
2020-10-28 07:21:29 +08:00
Renz Christian Bagaporo
1f2e2fe8af
soc: separate abstraction, description and implementation
2020-02-11 14:30:42 +05:00
Andrei Gramakov
4e8b4b9e49
soc: add USB peripheral register definitions, hal level, reg map, etc
2020-02-10 08:33:39 +00:00
Konstantin Kondrashov
739eb05bb9
esp32: add implementation of esp_timer based on TG0 LAC timer
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Closes: IDF-979
2020-02-06 14:00:18 +08:00
morris
e30cd361a8
global: rename esp32s2beta to esp32s2
2020-01-22 12:14:38 +08:00
