Mahavir Jain
22adc7ed75
Merge branch 'feat/secure_boot_ecdsa_p384' into 'master'
...
Support Secure Boot using ECDSA-P384 curve
Closes IDF-10016, IDF-10221, and IDF-12990
See merge request espressif/esp-idf!38517
2025-07-24 11:59:59 +05:30
harshal.patil
4fc9fd4891
fix(esp_system): Remove redundant crypto clock source selection
2025-07-21 09:19:42 +05:30
wuzhenghui
d7e1a747a6
fix(esp_hw_support): enable ESP_SLEEP_RTC_FAST_USE_XTAL_MODE only once in RTC_FAST selection
2025-07-18 15:29:07 +08:00
morris
c4d7b1cfce
refactor(uart)!: deprcated esp_rom_uart.h
2025-07-08 18:56:17 +08:00
wuzhenghui
5436d1f0c4
fix(esp_system): force enable uart0 sclk in esp_restart
2025-06-27 20:04:13 +08:00
Konstantin Kondrashov
ff0408c087
feat(esp_system): Adds Kconfigs to place code in IRAM
2025-06-23 13:23:33 +03:00
Laukik Hase
0d8a1f5427
refactor(hal): Refactor the APM LL/HAL APIs
2025-06-06 18:28:47 +05:30
wuzhenghui
113f40a3e0
feat(esp_hw_support): support gate PLL div clock source by reference count
2025-05-27 19:55:23 +08:00
wuzhenghui
34f249a28b
feat(esp_hw_support): support esp_perip_clk_init for esp32c5
2025-05-27 19:55:22 +08:00
harshal.patil
e08189f37b
fix(system_internal): Avoid the sec clock reset caused due to resetting all crypto peripherals
2025-05-22 16:01:02 +05:30
chaijie@espressif.com
24c46f1b89
refactor: move_ocode_to_pmu_init_c6_c5_c61
2025-05-20 11:08:35 +08:00
Mahavir Jain
55a2ad3df3
fix(esp_system): reset crypto peripherals before device restart
...
This change addresses a rare but critical issue observed on certain
ESP32-C3 and ESP32-S3 devices, where secure boot verification
intermittently fails due to improper cleanup of crypto peripherals
during a restart.
Background – Restart Behavior in IDF
------------------------------------
In ESP-IDF, when the device restarts (via `esp_restart()` or due to a
panic/exception), a partial peripheral reset is performed followed by a
CPU reset. However, until now, crypto-related peripherals were not
included in this selective reset sequence.
Problem Scenario
----------------
If a restart occurs while the application is in the middle of a bignum
operation (i.e., using the MPI/Bignum peripheral), the ROM code may
encounter an inconsistent peripheral state during the subsequent boot.
This leads to transient RSA-PSS secure boot verification failures.
Following such a failure, the ROM typically triggers a full-chip reset
via the watchdog timer (WDT). This full reset clears the crypto
peripheral state, allowing secure boot verification to succeed on the
next boot.
Risk with Aggressive Revocation
-------------------------------
If secure boot aggressive revocation is enabled (disabled by default in
IDF), this transient verification failure could mistakenly lead to
revocation of the secure boot digest.
If your product configuration has aggressive revocation enabled,
applying this fix is strongly recommended.
Frequency of Occurrence
-----------------------
The issue is rare and only occurs in corner cases involving
simultaneous use of the MPI peripheral and an immediate CPU reset.
Fix
---
This fix ensures that all crypto peripherals are explicitly reset prior
to any software-triggered restart (including panic scenarios),
guaranteeing a clean peripheral state for the next boot and preventing
incorrect secure boot behavior.
2025-04-15 19:06:26 +05:30
wuzhenghui
b3911c7c89
fix(esp_hw_support): fix unused OSC source deinit breaks XTAL32K configuration
2025-04-10 20:56:53 +08:00
wuzhenghui
c84757d35e
fix(esp_hw_support): fix current leakage if ext32k slow clock source not exists
2025-04-08 20:07:47 +08:00
Li Shuai
377914d579
change(esp_hw_support): fix wifi mac rx buffer link exception caused by pll clock
2025-01-17 17:16:39 +08:00
C.S.M
5e4fd8ee52
refactor(bod): Move brownout handling file from esp_system to esp_hw_support
2025-01-08 14:41:37 +08:00
Armando
784e87a9b2
feat(ocode): supported ocode on esp32c5
2025-01-02 10:12:47 +08:00
wuzhenghui
c067e406ce
fix(esp_system): deselect all modem modules clk source selection before clk init
2024-11-15 11:00:16 +08:00
Marius Vikhammer
9c5dde5536
refactor(panic): refactor and unify cache panic errors
2024-11-07 11:39:40 +08:00
Jiang Jiang Jian
1f47975472
Merge branch 'bugfix/idf-11064' into 'master'
...
fix some issues on esp32c5 eco1
Closes IDF-11064 and IDF-11066
See merge request espressif/esp-idf!34350
2024-11-04 20:46:01 +08:00
Li Shuai
45ea08b955
fix(esp_hw_support): fix the issue of wifi rx packet loss when switchng soc root clock source
2024-11-04 11:19:29 +08:00
Wu Zheng Hui
cceadc4ce8
Merge branch 'fix/fix_ota_slowclock_switching' into 'master'
...
fix(esp_hw_support): fix rtc slow clock missing after the OTA app changes the slow clock source
Closes IDF-11424
See merge request espressif/esp-idf!34416
2024-10-29 21:49:03 +08:00
wuzhenghui
7fdfa6c227
fix(esp_hw_support): disable unused clock sources after rtc clock switching complete
2024-10-28 15:57:26 +08:00
laokaiyao
ecb52d3af3
refactor(i2s): rename the confusing port number
2024-10-23 18:16:57 +08:00
wuzhenghui
04b2afed44
change(esp_hw_support): switch lp_cpu power mode with clock src to save lp_cpu working power
2024-09-26 11:23:06 +08:00
Marius Vikhammer
564d777018
Merge branch 'feature/lp_core_40_mhz' into 'master'
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feat(system): support choosing xtal as rtc-fast clock src on P4 and C5
Closes IDF-10203
See merge request espressif/esp-idf!32450
2024-09-20 10:57:15 +08:00
Marius Vikhammer
00eb97725b
feat(system): support choosing xtal as rtc-fast clock src on P4 and C5
...
With xtal as rtc-fast clock source the LP-Core can run at twice the default
clock frequency. 40 MHz as opposed to 20 MHz.
2024-09-19 17:30:44 +08:00
Alexey Lapshin
7498f4655a
fix(esp_system): fix GCC 14 analyzer warnings
2024-09-08 13:53:52 +07:00
C.S.M
e76c2c4b53
feat(brownout): Add brownout detector support on esp32c5
2024-08-22 11:26:30 +08:00
Armando
e58d608034
fix(cache): fixed cache panic init flow on psram board
2024-08-13 09:30:46 +08:00
Armando
190ea15839
feat(cache): supported cache panic on c5
2024-08-08 10:38:02 +08:00
Armando (Dou Yiwen)
0dd91afb09
Merge branch 'feat/c61_cache' into 'master'
...
cache: supported cache on c61
Closes IDF-9253 and DOC-8436
See merge request espressif/esp-idf!32407
2024-08-02 03:37:43 +08:00
Armando
67b8dbb5e5
feat(cache): supported cache on c61
2024-08-01 09:34:18 +08:00
Song Ruo Jing
6db52ffe12
remove(clk): rc32k is removed as a clk source option for lp_slow_clk on C5/C61
2024-07-31 22:41:23 +08:00
Song Ruo Jing
40f3bc2e57
feat(clk): Add basic clock support for esp32c5 mp
...
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
2024-06-26 14:26:34 +08:00
Xiao Xufeng
5b71b949be
fix(startup): move rtc initialization before MSPI timing tuning to improve stability
2024-06-18 01:16:24 +08:00
laokaiyao
21f870ecd5
remove(c5beta3): remove c5 beta3 system files
2024-06-17 12:02:15 +08:00
Song Ruo Jing
ac6101bf4e
feat(clk): support ESP32C5 XTAL 40M/48M selection
2024-06-11 17:42:43 +08:00
Lou Tianhao
3fb4909483
feat(example): support esp32c5 timer/gpio/uart wakeup
2024-04-10 11:45:04 +08:00
Marius Vikhammer
1c73c657c9
Merge branch 'ci/console_test_coverage' into 'master'
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ci(console): improve esp-system console test-coverage
Closes IDFCI-1856, IDF-9576, and IDF-9577
See merge request espressif/esp-idf!29748
2024-03-28 11:14:57 +08:00
Marius Vikhammer
42fc463c81
fix(console): fixed CONSOLE_NONE not working on C2/C3
2024-03-26 13:39:10 +08:00
Mahavir Jain
cdc1a2551b
Merge branch 'feature/enable_rsa_support_for_c5' into 'master'
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feat: enable RSA support for c5
See merge request espressif/esp-idf!29189
2024-03-22 10:10:47 +08:00
nilesh.kale
b11f286555
feat(esp_system/esp32c5): revised cypto clock to be used
...
This commit updated crypto clock to use 160M SPLL clock
2024-03-19 13:47:04 +05:30
laokaiyao
24d6dcb829
feat(esp32c5mp): add system related components
2024-03-18 17:34:56 +08:00
Konstantin Kondrashov
3f89072af1
feat(all): Use PRIx macro in all logs
2024-03-12 11:15:53 +02:00
Marius Vikhammer
4ce4af61ad
fix(system): update reset reasons for P4 and C5
2024-02-21 11:59:28 +08:00
Song Ruo Jing
d556fee5c4
Merge branch 'feature/esp32c5_clock_preliminary_support' into 'master'
...
Feature/esp32c5 clock preliminary support
See merge request espressif/esp-idf!28808
2024-02-08 11:54:35 +08:00
Song Ruo Jing
95133c179f
feat(clk): preliminary clock tree support for ESP32C5
2024-02-07 14:38:15 +08:00
liuning
3fa9c578f9
fix(clk): clear all lpclk source at clk init
2024-02-07 13:49:18 +08:00
laokaiyao
c0c6af99e9
fix(esp32c5): fixed the lack of crosscore ll on c5
2024-02-05 12:39:35 +08:00
