- Example CA certificates that are used for self-signed client certificates
need to include the Key Usage parameter.
- Python3.13 changed the default context of the SSL context that is
generated using ssl.create_default_context() by enabling the VERIFY_X509_STRICT
flag by default
This commit updates the following:
- Updates the panic handler to use only the RTC WDT to reset the system.
- Refactors some of the panic handler code.
- Updates Bluetooth files where in they now feed the WDTs instead of
reconfiguring them.
- Removes some unnecessary configuration of WDTs from various files.
- Added a unit test to verify that the system does not lock up when the
panic handler is stuck.
- Updates the memprot unit tests to work with the refactored panic
handler.
Closes https://github.com/espressif/esp-idf/issues/15166
Closes https://github.com/espressif/esp-idf/issues/15018
Closes https://github.com/espressif/esp-idf/issues/10110
Closes https://github.com/espressif/esp-idf/issues/13629
NMI interrupt level has been freed for all the Xtensa targets, making it possible
for the main application to use it. An example has been added to show how to
proceed.
This feature is useful for 3rd-party software to run GDB with predefined
options that described in project_description.json file
allow to pass custom options to "idf.py gdb":
--gdb-commands: command line arguments for gdb. (without changes)
-ex: pass command to gdb.
-x: pass gdbinit file to gdb. Alias for old --gdbinit command
Probably GCC-13.x and on-wards uses "-fmerge-constants" to merge
the const section (string/floating-point) across compilation units.
This makes it difficult to properly analyze the size output of rodata
section across libraries, the merged section (big in size) is showed
across a single library.
The config option added here can help to disable this compiler behavior
and help to provide better size analysis. It can be used during
development phase only as it increases rodata section size.
- As the PMA entry that made some memory regions cacheable was
assigned the highest priority, some intermediate inaccessible
memory regions bypassed protection.
- Added tests for the same
- Verified that even after changing the priority of the PMA entry,
a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address)
still needs the same number (29) of CPU cycles.
The implicit promise of heap_alloc_caps() and friends is that the memory it
returns is fit for the purpose as requested in the caps field. Before
this commit, that did not happen; e.g. DMA-capable memory wass returned
from a correct region, but not aligned/sized to something the DMA subsystem
can handle.
This commit adds an API to the esp_mm component that is then used by the
heap component to adjust allocation alignment, caps and size dependent on
the hardware requirement of the requested allocation caps.
