Commit Graph

774 Commits

Author SHA1 Message Date
Aditya Patwardhan
b39fb9f1d7 Merge branch 'fix/fix_bootloader_skip_validate_in_deep_sleep_v5.4' into 'release/v5.4'
fix(bootloader): fix signature verification skip in deep sleep scenarios (v5.4)

See merge request espressif/esp-idf!43697
2025-12-16 17:35:15 +05:30
Mahavir Jain
32b5c2ae14 fix(bootloader): fix signature verification skip in deep sleep scenario
For CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP enabled and exit from
deep sleep case the secure boot signature verification must be skipped
to improve the wakeup performance.

Closes https://github.com/espressif/esp-idf/issues/15590
2025-11-25 10:11:49 +05:30
Song Ruo Jing
aef9061d93 fix(console): release default console UART pins if console is switched in bootloader
Also print out console UART pin number in app cpu_startup stage

Closes https://github.com/espressif/esp-idf/issues/16764
Closes https://github.com/espressif/esp-idf/issues/17459
2025-11-22 17:52:31 +08:00
wuzhenghui
18475ffbe5 fix(esp_hw_support): add p4 rev3.0 MSPI workaround for deepsleep 2025-11-04 16:03:31 +08:00
armando
a70a29b7a6 feat(p4): p4 rev3 real chip support 2025-10-13 15:24:14 +08:00
armando
b3fd689da9 feat(esp32p4): support rev3 on fpga 2025-10-13 15:24:14 +08:00
harshal.patil
5fa0347a8b fix(bootloader_support): Allow pre-programmed XTS-AES psuedo round level efuses
- The API esp_flash_encryption_set_release_mode() by defualt programs
the XTS-AES pseudo round level efuse to level low but did not considered
any existing value that would have been programmed in the efuse bit.
2025-09-30 15:38:44 +05:30
harshal.patil
b40f14cff6 fix(bootloader_support): Reorder write protection bits of some shared security efuses 2025-09-30 15:37:25 +05:30
Jiang Jiang Jian
3ad2b49d80 Merge branch 'bugfix/encrypt_len_for_sb_update_case_v5.4' into 'release/v5.4'
fix(bootloader): correct encryption length for secure update without secure boot (v5.4)

See merge request espressif/esp-idf!41924
2025-09-19 03:22:17 +08:00
Mahavir Jain
0bddd778a9 fix(bootloader): correct encryption length for secure update without secure boot
For secure update without secure boot case, the encryption length for
app image must consider signature block length as well. This was
correctly handled for secure boot case but not for secure update without
secure boot.
2025-09-16 10:20:26 +05:30
gaoxu
ac47fca1db fix(adc): fix rng adc error after deep sleep 2025-07-25 10:22:16 +08:00
nilesh.kale
497fc7ed18 feat: enabled ECDSA-P192 support for ESP32H2 2025-07-09 13:05:56 +08:00
Omar Chebib
fd7cfe0b04 fix(esp_system): fix RTC reserved area alignment in the linker script
Make sure the size of the RTC reserved area complies with the alignment requirement.

Closes https://github.com/espressif/esp-idf/issues/13082
2025-05-27 11:20:07 +08:00
Mahavir Jain
09fbed0eec fix: secure OTA without secure boot issue for MMU page size configurable SoCs
For secure app verification during OTA update case, the image was
getting memory mapped twice and hence the failure in verification.

Modified from memory mapped flash read to SPI flash read approach
for the MMU page size from image header.

Regression from 07318a4987

Closes https://github.com/espressif/esp-idf/issues/15936
2025-05-14 10:55:48 +05:30
armando
0255950b63 fix(bootloader): fixed image cannot exceed 16MB issue
flash 32-bit-addr is an experimental feature that has multiple
dependencies, e.g. flash chip vendor, etc.

If CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH can be enabled
successfully and tests are passed, we can allow images to be
placed on higher-than-16MB flash addresses
2025-04-30 10:33:10 +08:00
gaoxu
d74f12dea7 feat(adc): support ADC calibration on ESP32P4 2025-04-01 15:07:56 +08:00
gaoxu
3e9c1ae62b fix(adc): fix adc1 error after bootloader random 2025-04-01 15:05:31 +08:00
harshal.patil
0076bb0289 fix(secure_boot): Fix SB verification failure when sig block and key digest mismatch
- Secure boot V2 verification failed when multiple keys are used to sign the bootloader
  and the application is signed with a key other than the first key that is used to
  sign the bootloader.
- The issue was introduced as a regression from the commit `ff16ce43`.
2025-03-05 11:26:33 +05:30
harshal.patil
b06a4c198a feat(bootloader_support): Permanently enable XTS-AES pseudo rounds when FE release mode is enabled 2025-01-21 12:28:23 +05:30
laokaiyao
889537960e refactor(lpperi): improve compatibility solution 2025-01-16 10:21:17 +08:00
laokaiyao
25f64d9cbd refactor(lpperi): compatible refactor for H2 ECO5 2025-01-13 14:36:00 +08:00
Song Ruo Jing
192f01c65f fix(esp_system): hp periph clk should not be gated on core/system reset 2024-12-12 21:03:37 +08:00
Jiang Jiang Jian
023d772d90 Merge branch 'bugfix/chip823_pll_bug_v5.4' into 'release/v5.4'
fix(H2):fix pll low temp bug(v5.4)

See merge request espressif/esp-idf!35242
2024-11-29 10:47:55 +08:00
zlq
7a92f14df6 fix(H2):fix pll low temp bug 2024-11-27 17:46:10 +08:00
Laukik Hase
9d7a4e5917 change(bootloader): Map only the necessary length when fetching the app description struct 2024-11-21 15:12:55 +05:30
Mahavir Jain
07318a4987 feat(bootloader): add support to use MMU page size from app binary
For the SoCs that support configurable MMU page size, it is possible
that the bootloader and application are built with different MMU page
size configuration. This mismatch is not supported at the moment and
application verification fails (at bootup or during OTA update).

Configuring MMU page size helps to optimize the flash space by having
smaller alignment and padding (secure) requirements. Please note that
the MMU page size is tied with the flash size configuration at the
moment (`ESPTOOLPY_FLASHSIZE_XMB`).

This MR ensures that application verification happens using the MMU page
size configured in its binary header. Thus, bootloader and application
can now have different MMU page sizes and different combinations shall
be supported.
2024-11-21 15:11:38 +05:30
Aditya Patwardhan
82db0feab2 fix(security): Update key manager specific initializations for esp32c5 2024-10-28 11:13:43 +08:00
Jiang Jiang Jian
88317cff24 Merge branch 'feat/pwr_glitch_bringup_c5_c61' into 'master'
feat(pwr_glitch): Add power glitch reset support on esp32c5, esp32c61

See merge request espressif/esp-idf!33032
2024-10-15 14:15:49 +08:00
zhoupeng
858d0647e8 fix(pwr_glitch): Add Comment and only add power glitch reset support on esp32c5 ECO0 2024-10-09 11:08:38 +08:00
chaijie@espressif.com
e1423c53d5 feat(pwr_glitch): Add power glitch support on esp32c5/esp32c61 2024-10-08 11:44:21 +08:00
Konstantin Kondrashov
d5f37b526d feat(partitions): Adds new partition types and subtypes for bootloader and partition_table 2024-10-01 14:22:22 +03:00
Mahavir Jain
336f938110 fix(bootloader): self encryption workflow in bootloader not working on C5
Added explicit wait for key manager state to be idle before configuring
the register for flash encryption key usage from efuse. This now ensures
that flash contents are encrypted using efuse programmed key.

Also refactored code a bit to move into target specific directory.
2024-09-25 14:21:16 +05:30
Mahavir Jain
a71e0fc028 Merge branch 'feature/enable_sha_support_for_esp32c61' into 'master'
feat: enable support for sha peripheral in esp32c61

Closes IDF-9234

See merge request espressif/esp-idf!32830
2024-09-20 13:22:14 +08:00
Sachin Billore
b4749b88d9 feat(APM): Add APM APIs for ESP32-C61 2024-09-19 11:07:42 +05:30
Konstantin Kondrashov
e8dab4c257 Merge branch 'feature/esp32c61_update_efuses' into 'master'
feat(efuse): Updates efuse table for esp32c61

Closes IDF-11057 and IDF-9282

See merge request espressif/esp-idf!33436
2024-09-12 01:20:20 +08:00
nilesh.kale
12fc7a677e feat: enable support for sha peripheral in esp32c61 2024-09-11 14:49:01 +05:30
wuzhenghui
05e74480f5 feat(esp_system): gate some clock by default to optmize esp32p4 active power 2024-09-11 10:53:00 +08:00
Konstantin Kondrashov
8539760e79 feat(efuse): Updates efuse table for esp32c61 2024-09-10 14:16:29 +03:00
Armando
42cf1d8867 fix(mspi): fixed mspi clock wrong on ram loadable app on c5 2024-09-10 11:12:02 +08:00
Armando
6933ba39bc fix(system): fixed ram loadable app on p4 2024-09-09 10:31:48 +08:00
Armando
8842e5764f feat(psram): xip psram c5 2024-09-03 18:17:03 +08:00
Song Ruo Jing
b6916ca304 Merge branch 'bugfix/custom_console_uart_pins_c5_c61' into 'master'
fix(uart): make custom console uart TX/RX pins same to the default console uart pins

See merge request espressif/esp-idf!33110
2024-09-02 21:26:56 +08:00
Song Ruo Jing
8e53e91ec9 fix(uart): make custom console uart pins same to the default console uart pins 2024-09-02 15:24:29 +08:00
Aditya Patwardhan
d1c47835a2 fix(security): Fixed flash encryption for esp32p4
The flash encryption on esp32p4 was broken due to some code related
    to key manager not being executed when key manager support was
    disabled on esp32p4 target.
    This commit fixes that behaviour
    Additionally, the atomic env enablement for
    key_mgr_ll_enable_peripheral_clock was fixed.
2024-09-02 14:00:55 +08:00
Lou Tianhao
4393343ac9 fix(ci): some actions taken to pass ci 2024-08-29 14:15:41 +08:00
laokaiyao
1c2f8b8ce0 feat(bootloader): support to check efuse block revision
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
2024-08-26 10:02:31 +08:00
C.S.M
8078ad7840 feat(brownout): Add brownout detector support on esp32c61 2024-08-22 11:26:30 +08:00
C.S.M
e76c2c4b53 feat(brownout): Add brownout detector support on esp32c5 2024-08-22 11:26:30 +08:00
Song Ruo Jing
7b510049fb fix(ci): esp32 build failure due to bootloader size too large 2024-08-19 19:08:10 +08:00
Nilesh Kale
6028332164 Merge branch 'feature/enable_secure_boot_in_esp32c61' into 'master'
feat: enable secure boot feature for esp32c61

Closes IDF-9233

See merge request espressif/esp-idf!31420
2024-08-13 19:23:53 +08:00