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3 Commits

Author SHA1 Message Date
Angus Gratton
420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00
Shubham Kulkarni
e1c0fb0c62 log: Check for ISR context and use proper API to get Tick Count 2020-02-07 04:49:53 +00:00
Ivan Grokhotkov
676b5e0deb log: refactoring to make compatible with no-FreeRTOS builds 2019-11-22 11:41:35 +01:00