Xiao Xufeng
08f5f0d66b
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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This reverts commit 7145fc9558
2025-12-24 02:31:57 +08:00
Xiao Xufeng
187f43a3bb
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"
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This reverts commit 3c5d2e6b58
2025-12-17 03:33:30 +08:00
armando
cdff2570c7
ci(p4): disable p4 rev3 invalid tests temporarily
2025-11-20 11:33:36 +08:00
Jiang Jiang Jian
376f396e20
Merge branch 'bugfix/esp32c5_encrypted_flash_write_v5.5' into 'release/v5.5'
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fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v5.5)
See merge request espressif/esp-idf!43326
2025-11-17 15:02:40 +08:00
Mahavir Jain
3fd00b4d80
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.
This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
2025-11-13 13:26:06 +05:30
harshal.patil
6ea63548d4
fix(esp_security): Set WR_DIS_SECURE_BOOT_SHA384_EN by default when
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Flash Encryption Release mode is enabled and Secure Boot P384 scheme not is enabled.
2025-11-11 17:53:04 +05:30
harshal.patil
7b57a1cd16
fix(esp_security): Fix undefined efuse build failure in case of ESP32-P4
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- The `wr_dis` efuse bit corresponding to `SECURE_BOOT_SHA384_EN` is absent in P4
2025-11-11 17:53:04 +05:30
Mahavir Jain
042f29dd66
Merge branch 'fix/change_write_protection_bit_of_shared_security_efuses_v5.5' into 'release/v5.5'
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Reorder write protection bits of some shared security efuses (v5.5)
See merge request espressif/esp-idf!42033
2025-10-15 09:38:59 +05:30
harshal.patil
6ab5a2f883
fix(esp_security): Configure the Key Manager to use XTS-AES efuse key by-default
2025-10-13 10:40:50 +05:30
harshal.patil
70a8b4d842
fix(bootloader_support): Reorder write disabling ECDSA_CURVE_MODE
2025-10-13 10:40:16 +05:30
harshal.patil
d902072d80
fix(bootloader_support): Reorder write protection bits of some shared security efuses
2025-10-13 10:40:16 +05:30
harshal.patil
ae7d7542e0
fix(esp_key_mgr): Fix incorrect key manager state management
2025-09-12 17:26:27 +05:30
harshal.patil
f6f15bf91a
change(mbedtls/ecdsa): The ECDSA module of ESP32-H2 ECO5 does not use MPI module
2025-08-13 18:53:19 +05:30
Jiang Jiang Jian
3c39b32195
Chip/support esp32c61 v5.5
2025-07-22 12:21:36 +08:00
nilesh.kale
c65858287a
feat: enabled secure boot support esp32h21
2025-04-25 17:48:25 +05:30
Laukik Hase
fc4802c0d6
feat(esp_tee): Protect the HMAC and DS peripherals from REE access
2025-04-16 19:19:04 +05:30
Laukik Hase
1c4969bc47
feat(esp_security): Add a TEE-specific crypto lock layer with stub implementations
2025-04-16 19:19:03 +05:30
nilesh.kale
aae4bfb6f3
feat: enable ecdsa support for esp32h21
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This commit enabled suppot for ECDSA peripheral in ESP32H21.
2025-04-14 10:26:46 +05:30
Laukik Hase
bd314c2460
refactor(esp_tee): Update the SHA clock configuration service call
2025-04-04 10:31:28 +05:30
Laukik Hase
3e95020c59
refactor(esp_security): Introduce dedicated APIs for crypto clock configuration
2025-04-04 10:31:27 +05:30
Mahavir Jain
ce7ec7f19f
Merge branch 'feature/enable_hmac_and_ds_support_for_esp32h21' into 'master'
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feat: enabled hmac and ds support in esp32h21
Closes IDF-11495 and IDF-11497
See merge request espressif/esp-idf!37085
2025-03-21 17:23:46 +08:00
Chen Jichang
45ba78940f
feat(esp32h4): finnal introduce hello world
2025-03-19 18:48:41 +08:00
nilesh.kale
f794eb9b2d
feat: enabled hmac and ds support in esp32h21
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This commit enables support for HMAC and DS in ESP32H21
2025-03-13 10:23:11 +05:30
igor.udot
daf2d31008
test: format all test scripts
2025-03-05 12:08:48 +08:00
Chen Jichang
6f83f39dce
feat(esp32h4): introduce target esp32h4(stage 1)
2025-02-08 17:07:44 +08:00
laokaiyao
9269b785f8
refactor(ecdsa): rely on efuse to get chip revision
2025-01-24 11:50:17 +08:00
Aditya Patwardhan
d8d9ba3dc2
fix(soc): Fixed ECDSA register compatibility
2025-01-24 11:50:17 +08:00
Aditya Patwardhan
bef2a72ecb
fix(hal): Make the ECDSA countermeasure dynamically applicable
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This commit makes the ECDSA countermeasure dynamically applicable
across different revisions of the ESP32H2 SoC.
2025-01-24 11:50:17 +08:00
Mahavir Jain
6875cbf022
feat(ecc): enable ECC constant time mode for ESP32-H2 ECO5
2025-01-24 11:50:17 +08:00
Gao Xu
54f501a2fc
Merge branch 'feat/h21_introduce_step8' into 'master'
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feat(esp32h21): introduce hello world to ESP32H21 (stage8)
See merge request espressif/esp-idf!35874
2024-12-31 10:39:21 +08:00
gaoxu
25731d0c1e
feat(esp32h21): finnal introduce hello world support
2024-12-30 20:14:40 +08:00
Marek Fiala
2c814ef2fa
feat(tools): Enforce utf-8 encoding with open() function
2024-12-27 17:12:21 +08:00
gaoxu
64bbb53b8f
feat(esp32h21): introduce target esp32h21(stage 1)
2024-11-12 15:42:27 +08:00
Aditya Patwardhan
82db0feab2
fix(security): Update key manager specific initializations for esp32c5
2024-10-28 11:13:43 +08:00
harshal.patil
c2b71a3855
ci(mbedtls): Fix component dependencies for security-related test apps
2024-10-24 14:45:56 +05:30
Laukik Hase
5328dcd00c
change(build): Add a new CMake flag NON_OS_BUILD for non-FreeRTOS builds
2024-10-21 19:03:30 +05:30
harshal.patil
e12c261b1b
ci(esp_security): Add config to enable FPGA-related tests
2024-10-09 09:46:19 +05:30
harshal.patil
9e3a846356
ci(esp_security): Enable crypto drivers test app build only for supported targets
2024-10-09 09:46:18 +05:30
Mahavir Jain
e52e2d282a
refactor(startup): move key manager specific code to esp_security component
2024-09-25 14:21:19 +05:30
harshal.patil
e1cd5b909e
fix(esp_security): Fix build failure when dpa protection at startup is disabled
2024-09-20 18:46:55 +05:30
harshal.patil
39872a5575
feat(esp_security): Config to forcefully enable ECC constant-time operations during bootup
2024-09-20 18:46:55 +05:30
Mahavir Jain
a71e0fc028
Merge branch 'feature/enable_sha_support_for_esp32c61' into 'master'
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feat: enable support for sha peripheral in esp32c61
Closes IDF-9234
See merge request espressif/esp-idf!32830
2024-09-20 13:22:14 +08:00
Mahavir Jain
fd192e0e9e
Merge branch 'fix/ds_tries_acquiring_mpi_lock_twice' into 'master'
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Clean up DS trying to re-acquire MPI lock post common crypto lock layer
See merge request espressif/esp-idf!33056
2024-09-12 12:18:22 +08:00
nilesh.kale
12fc7a677e
feat: enable support for sha peripheral in esp32c61
2024-09-11 14:49:01 +05:30
wanckl
4e095f4b9f
ci(esp32c61): enable c61 generic target test
2024-09-02 19:26:12 +08:00
harshal.patil
3b97011e39
fix(esp_security/ds): Clean up DS trying to re-acquire MPI lock post common crypto lock layer
2024-08-23 17:53:55 +05:30
Mahavir Jain
79f9c7d157
feat(esp_security): Move DS, HMAC, DPA and crypto lock implementation
2024-08-20 12:35:22 +08:00
Mahavir Jain
262f27290b
feat(esp_security): move the crypto test app to new esp_security component
2024-08-20 12:35:22 +08:00
harshal.patil
57db17bec2
feat(esp_security/crypto): Create a generic crypto locking layer across targets
2024-08-20 12:35:22 +08:00
harshal.patil
488b2a741d
change(esp_security): Move the crypto locking layer into the security component
2024-08-20 12:35:22 +08:00
