For secure app verification during OTA update case, the image was
getting memory mapped twice and hence the failure in verification.
Modified from memory mapped flash read to SPI flash read approach
for the MMU page size from image header.
Regression from 07318a4987
Closes https://github.com/espressif/esp-idf/issues/15936
flash 32-bit-addr is an experimental feature that has multiple
dependencies, e.g. flash chip vendor, etc.
If CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH can be enabled
successfully and tests are passed, we can allow images to be
placed on higher-than-16MB flash addresses
- Secure boot V2 verification failed when multiple keys are used to sign the bootloader
and the application is signed with a key other than the first key that is used to
sign the bootloader.
- The issue was introduced as a regression from the commit `ff16ce43`.
For the SoCs that support configurable MMU page size, it is possible
that the bootloader and application are built with different MMU page
size configuration. This mismatch is not supported at the moment and
application verification fails (at bootup or during OTA update).
Configuring MMU page size helps to optimize the flash space by having
smaller alignment and padding (secure) requirements. Please note that
the MMU page size is tied with the flash size configuration at the
moment (`ESPTOOLPY_FLASHSIZE_XMB`).
This MR ensures that application verification happens using the MMU page
size configured in its binary header. Thus, bootloader and application
can now have different MMU page sizes and different combinations shall
be supported.
Added explicit wait for key manager state to be idle before configuring
the register for flash encryption key usage from efuse. This now ensures
that flash contents are encrypted using efuse programmed key.
Also refactored code a bit to move into target specific directory.
The flash encryption on esp32p4 was broken due to some code related
to key manager not being executed when key manager support was
disabled on esp32p4 target.
This commit fixes that behaviour
Additionally, the atomic env enablement for
key_mgr_ll_enable_peripheral_clock was fixed.
This configuration bit is required for ADC operation as well and hence
should not be cleared in the RNG API sequence.
Ideally, the ADC driver should take care of initializing this bit but
still the RNG layer change is required because of interleaved API usage
scenario described in following linked issue.
Closes https://github.com/espressif/esp-idf/issues/14124
Closes https://github.com/espressif/esp-idf/issues/14280
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
