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1646 Commits

Author SHA1 Message Date
Jiang Jiang Jian
f409428bf3 Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0' 
fix(spi_flash): Add CPU frequency switching during flash encrypted write (v6.0)

See merge request espressif/esp-idf!44304
 2025-12-21 15:28:33 +08:00
Jiang Jiang Jian
ac1e81f980 Merge branch 'fix/esp32p4_eco5_multicore_wfi_autoclock_gating_v6.0' into 'release/v6.0' 
fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore (v6.0)

See merge request espressif/esp-idf!44255
 2025-12-21 15:22:15 +08:00
Xiao Xufeng
469953bd04 Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" 
This reverts commit 3c5d2e6b58.
 2025-12-17 01:21:46 +08:00
Xiao Xufeng
ae7124abe3 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-17 01:21:45 +08:00
Chen Chen
1b015d22eb refactor(esp_system): clear dependency on hal components 2025-12-16 09:11:59 +08:00
Samuel Obuch
5908c9574c fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore 2025-12-15 14:47:54 +01:00
morris
5c5d78b639 Merge branch 'ci/freertos_header_v6.0' into 'release/v6.0' 
ci(header_check): Add check for public header should not include freertos  (backport v6.0)

See merge request espressif/esp-idf!44104
 2025-12-11 18:00:57 +08:00
morris
946dcf73e3 Merge branch 'feature/graduate_i2s_parlio_analog_hal_components_v6.0' into 'release/v6.0' 
Feature/graduate i2s parlio analog hal components v6.0

See merge request espressif/esp-idf!44043
 2025-12-11 16:58:37 +08:00
Jiang Jiang Jian
3df1ee13fb Merge branch 'fix/fix_mspi_write_stuck_after_reset_v6.0' into 'release/v6.0' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 (v6.0)

See merge request espressif/esp-idf!43994
 2025-12-11 13:59:25 +08:00
laokaiyao
e964c74618 feat(hal): graudate the parlio hal driver into a new component 2025-12-11 10:26:05 +08:00
laokaiyao
73ebd544fd refactor(i2s): refactor of the private i2s caps 2025-12-11 10:25:42 +08:00
C.S.M
ed64e7bf78 ci(header_check): Add check for public header should not include freertos 2025-12-10 15:10:43 +08:00
morris
37c614d626 feat(twai): graduate the hal drivers into esp_hal_twai component 2025-12-10 13:56:47 +08:00
wuzhenghui
01ec965252 fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 2025-12-10 12:21:55 +08:00
morris
4ca7b95d83 Merge branch 'refactor/esp_hal_gpio_v6.0' into 'release/v6.0' 
refactor(gpio): split GPIO HAL into separate component (v6.0)

See merge request espressif/esp-idf!43895
 2025-12-09 16:02:49 +08:00
Alexey Gerenkov
effa1e4248 Merge branch 'feature/update-toolchain-to-esp-15.2.0_20250929.4-6d3fdb7_v6.0' into 'release/v6.0' 
Make Picolibc the default libc (v6.0)

See merge request espressif/esp-idf!43966
 2025-12-08 18:13:08 +08:00
Song Ruo Jing
62899cbba6 refactor(gpio): split GPIO HAL into separate component 
cleaned up some includes in GPIO peripheral files
 2025-12-08 14:33:26 +08:00
Jiang Jiang Jian
c33b848fea Merge branch 'bugfix/fix_chip_hangup_v6.0' into 'release/v6.0' 
bugfix: clear regdma status when restart V6.0

See merge request espressif/esp-idf!43908
 2025-12-08 11:07:25 +08:00
Alexey Lapshin
ad7f4b9670 feat(esp_libc): make picolibc default libc 2025-12-06 00:08:35 +07:00
morris
0e6525a97c Merge branch 'bugfix/uart_related_backports_v6.0' into 'release/v6.0' 
fix(uart): some related uart backports (v6.0)

See merge request espressif/esp-idf!43612
 2025-12-02 17:40:25 +08:00
sibeibei
e5fb2f50ec bugfix: clear regdma status when restart 2025-12-02 10:31:58 +08:00
Sudeep Mohanty
216bca7dd3 ci(esp_system): Re-enable esp_system tests for esp32p4 2025-11-27 15:07:29 +05:30
Roland Dobai
093c5f0b01 Merge branch 'fix/core_system_fixes_for_p4_eco5_v6_0' into 'release/v6.0' 
Core System fixes for p4 eco5 (v6.0)

See merge request espressif/esp-idf!43629
 2025-11-27 10:15:03 +01:00
Song Ruo Jing
1067b313c6 fix(uart): fix some wdt get triggered due to uart sclk not exist on C5 
Interrupt wdt would get triggered on uart_driver_install if uart driver was deleted before
Closes https://github.com/espressif/esp-idf/issues/17779

RTC wdt would get triggered on esp_restart if uart driver was deleted before
 2025-11-27 11:08:48 +08:00
armando
dfe4a6e5f7 feat(hal):graudate the camera hal driver into a new component 2025-11-26 08:42:12 +08:00
Marius Vikhammer
72c7bfe2e2 fix(system): fixed constructors not working properly on P4 ECO5 2025-11-25 13:35:51 +05:30
Marius Vikhammer
02b891f9de fix(lp-core): fixed rtc mem conflict on p4 eco5 between app and ULP 2025-11-25 13:35:50 +05:30
morris
72159c2361 Merge branch 'feat/esp_hal_pcnt_v6.0' into 'release/v6.0' 
feat(hal): graudate the PCNT hal driver into a new component (v6.0)

See merge request espressif/esp-idf!43444
 2025-11-24 22:35:51 +08:00
morris
45fa560e98 Merge branch 'feat/make_p4_rev3_default_v6.0' into 'release/v6.0' 
p4: make v3 as default (v6.0)

See merge request espressif/esp-idf!43440
 2025-11-21 15:12:44 +08:00
morris
f050c1deb1 Merge branch 'fix/no_function_call_in_min_max_v6.0' into 'release/v6.0' 
refactor: avoid function calls inside MIN/MAX macros (v6.0)

See merge request espressif/esp-idf!43476
 2025-11-21 12:03:09 +08:00
Chen Jichang
c84773f307 feat(hal): graudate the PCNT hal driver into a new component 2025-11-21 11:22:41 +08:00
armando
714b022a43 ci(p4): disable p4 rev3 invalid tests temporarily 2025-11-21 02:48:05 +00:00
morris
8242e6914b Merge branch 'feature/ledc_etm_support_v6.0' into 'release/v6.0' 
feat(ledc): add ETM support for LEDC peripheral (v6.0)

See merge request espressif/esp-idf!43401
 2025-11-21 10:38:11 +08:00
Mahavir Jain
888e92c7d6 Merge branch 'feat/esp_tee_c61_v6.0' into 'release/v6.0' 
feat(esp_tee): Support for ESP32-C61 (v6.0)

See merge request espressif/esp-idf!43461
 2025-11-20 10:57:00 +05:30
Jiang Jiang Jian
3584d2273e Merge branch 'feat/support_p4_unicore_auto_clock_gating_v6.0' into 'release/v6.0' 
feat(esp_hw_support): support unicore auto clock gating for esp32p4 rev3+ (v6.0)

See merge request espressif/esp-idf!43368
 2025-11-20 10:32:40 +08:00
Laukik Hase
2cb0fa5c34 feat(esp_tee): Support for ESP32-C61 - the rest of the components 2025-11-19 10:57:42 +05:30
morris
e9539d4560 refactor: avoid function calls inside MIN/MAX macros 2025-11-18 15:18:14 +08:00
Jiang Jiang Jian
6472c8215a Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0' 
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v6.0)

See merge request espressif/esp-idf!43325
 2025-11-18 12:27:21 +08:00
Song Ruo Jing
88a183345b fix(console): wrong uart console pin info when UART console is not used 2025-11-14 20:58:17 +08:00
Jiang Jiang Jian
7738347885 Merge branch 'fix/fix_xtal32k_power_breaks_adc_v6.0' into 'release/v6.0' 
fix(esp_system): fix XTAL32K power breaks ADC function on 32k XTAL clock pin (v6.0)

See merge request espressif/esp-idf!43295
 2025-11-14 16:49:54 +08:00
Jiang Jiang Jian
86d09a29c6 Merge branch 'fix/esp32p4_rev3_hardware_issue_workarounds_v6.0' into 'release/v6.0' 
fix(esp_hw_support): esp32p4 eco5 hardware issues workaround (v6.0)

See merge request espressif/esp-idf!42941
 2025-11-14 16:47:24 +08:00
morris
cc5bad7e39 Merge branch 'feature/esp32p4_eco5_io_hold_v6.0' into 'release/v6.0' 
feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 (v6.0)

See merge request espressif/esp-idf!43307
 2025-11-14 15:51:25 +08:00
wuzhenghui
5137558961 feat(esp_hw_support): support unicore auto clock gating for esp32p4 rev3+ 2025-11-14 14:06:23 +08:00
Alexey Gerenkov
ccc59ed681 Merge branch 'esp_tracing_component_v6.0' into 'release/v6.0' 
New Esp tracing component (v6.0)

See merge request espressif/esp-idf!43059
 2025-11-13 17:44:25 +08:00
Mahavir Jain
0f77374746 fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption 
Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.

This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
 2025-11-13 13:25:57 +05:30
Song Ruo Jing
05c2486d8b fix(clk): 400MHz CPU should still be selectable on ESP32-P4 less than rev3 2025-11-12 22:28:03 +08:00
wuzhenghui
a7063c9884 fix(esp_system): fix XTAL32K power breaks ADC function on 32k XTAL clock pin 2025-11-12 19:03:42 +08:00
wuzhenghui
5eff18eec2 fix(esp_hw_support): add p4 rev3.0 MSPI workaround for deepsleep 2025-11-11 21:58:51 +08:00
Chen Chen
ed64a767ef refactor(mcpwm): make mcpwm_hal independent & cleanup soc_caps 2025-11-10 10:47:10 +08:00
Erhan Kurubas
dcde633acd feat(tracing): add new component for tracing 2025-11-05 09:57:18 +01:00