Applicable for chips affected by interrupt issue:
- ESP32C5
- ESP32C61
- ESP32H4
For all other chips that support the ZCMP extension without issues,
it will be enabled unconditionally.
Allow to disable implicit inlining of constexpr functions from libstdc++.
This is a known GCC issue https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93008
that may affect C++ application size depending on its structure.
- Dynamically switch the AES operation modes based on the buffer operating length
- Shorter AES and SHA operations can now run faster and concurrently as well
Closes https://github.com/espressif/esp-idf/issues/15914
The following updates have been made in this commit:
- The commit places ring buffer code in flash memory by default.
- CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH has been removed.
- CONFIG_RINGBUF_IN_IRAM is added and can be used to restore the
previous memory placement.
The following updates have been made in this commit:
- The commit places FreeRTOS code in flash memory by default.
- CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH has been removed.
- CONFIG_FREERTOS_IN_IRAM is unhidden and can be used to restore the
previous memory placement.
- A test has been added for users to conduct performance impact testing
based on memory placement configurations.
This option replaces implementations of functions from ROM:
- memcpy
- memcmp
- memmove
- str[n]cpy
- str[n]cmp
The functions used in the firmware will be better optimized for misaligned
memory. Here are some measurements in CPU cycles for 4096-byte buffers:
memcpy: 28676 -> 4128
memcmp: 49147 -> 14259
memmove: 33896 -> 8086
strcpy: 32771 -> 17313
strcmp: 32775 -> 13191
The documentation for the IDF Size tool has been relocated from the
performance section to the tools section and updated to reflect the
current refactored version of esp-idf-size.
Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
in speed.rst:
- add startup time increase info when spiram test is enabled
- add startup time increase info when spiram is enabled and
poisoning comprehensive is enabled
- add L2 cache variable size info to optimize IRAM space / cache misses
- update sections refencing bluetooth/wifi built-in tasks to not show
related info for p4 targets.
- Add IDF_TARGET_RF_TYPE for esp32c5
in ram-usage.rst:
- add L2 cache variable size info to maximize RAM space
Remove the files from esp32c5.txt and esp32p4.txt
that are no longer in need of update.
