9 Commits

Author	SHA1	Message	Date
Marius Vikhammer	00eb97725b	feat(system): support choosing xtal as rtc-fast clock src on P4 and C5 ... With xtal as rtc-fast clock source the LP-Core can run at twice the default clock frequency. 40 MHz as opposed to 20 MHz.	2024-09-19 17:30:44 +08:00
Song Ruo Jing	6db52ffe12	remove(clk): rc32k is removed as a clk source option for lp_slow_clk on C5/C61	2024-07-31 22:41:23 +08:00
Song Ruo Jing	335d39b869	feat(clk): Add basic clock support for esp32c61 ... - Support SOC ROOT clock source switch - Support CPU frequency change - Support RTC SLOW clock source switch - Support RTC SLOW clock + RC FAST calibration - Remove FPGA build	2024-07-31 22:41:22 +08:00
laokaiyao	c731b099ee	remove(c5beta3): remove c5 beta3 doxy files	2024-06-17 12:02:15 +08:00
laokaiyao	21f870ecd5	remove(c5beta3): remove c5 beta3 system files	2024-06-17 12:02:15 +08:00
Linda	52cfd1bf24	docs: fix clock sources for esp32c6	2024-05-07 17:35:39 +08:00
laokaiyao	24d6dcb829	feat(esp32c5mp): add system related components	2024-03-18 17:34:56 +08:00
hongshuqing	d78805670a	fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug	2024-03-05 19:33:30 +08:00
laokaiyao	a48f4760d2	feat(esp32c5): add system related supports	2024-01-02 11:17:11 +08:00