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34,571 Commits 22 Branches 170 Tags
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Commit Graph

446 Commits

Author SHA1 Message Date
wuzhenghui
c6731c0d53 fix(esp_hw_support): fix current leakage if ext32k slow clock source not exists 2025-04-16 15:05:57 +08:00
Geng Yuchao
e0113f246d feat(ble):Support Bluetooth LE 5.1 direction finding feature 2025-03-26 16:31:39 +08:00
Jiang Jiang Jian
b25bf99d4f Merge branch 'feat/spi_std_timing_and_bit_trans_v5.1' into 'release/v5.1' 
feat(driver_spi): support adjust master rx to standard timing (v5.1)

See merge request espressif/esp-idf!36402
 2025-01-24 15:11:09 +08:00
laokaiyao
fdd16ba44f refactor(ecdsa): rely on efuse to get chip revision 2025-01-24 09:13:36 +05:30
Aditya Patwardhan
151b6e9be5 fix(soc): Fixed ECDSA register compatibility 2025-01-24 09:13:35 +05:30
Mahavir Jain
58e5f48368 feat(ecc): enable ECC constant time mode for ESP32-H2 ECO5 2025-01-23 22:10:21 +05:30
wanckl
caf0d04a31 feat(driver_spi): support using SPI_DEVICE_STD_TIMING to adjust master rx in standard timing 2025-01-22 11:14:23 +08:00
harshal.patil
a29dadbabc feat(hal/spi_flash_encrypted): Enable pseudo rounds function during XTS-AES operations 2025-01-17 14:20:05 +05:30
harshal.patil
b9fe639725 feat(hal/aes): Enable pseudo rounds function during AES operations 2025-01-17 14:01:43 +05:30
laokaiyao
39279e589d refactor(lpperi): improve compatibility solution 2025-01-15 17:16:19 +08:00
laokaiyao
dce7c47e72 refactor(lpperi): compatible refactor for H2 ECO5 2025-01-15 11:49:42 +08:00
Konstantin Kondrashov
ace6ef9786 feat(espefuse): Adds efuses for esp32h2 eco5 
- Support efuses that are not present in the main efuse table
 2025-01-08 12:21:45 +02:00
Michael (XIAO Xufeng)
fd3da18412 Merge branch 'bugfix/warn_rc32k_use_in_kconfig_v5.1' into 'release/v5.1' 
fix(clk): add an inevitable kconfig option to be selected to use rc32k (v5.1)

See merge request espressif/esp-idf!35967
 2025-01-07 15:19:10 +08:00
C.S.M
7f6b2d3917 fix(bod): Improve esp32h2 brownout handling 2024-12-30 12:05:13 +08:00
morris
c7ad441eab Merge branch 'bugfix/rtc_clk_cpu_freq_set_xtal_behavior_v5.1' into 'release/v5.1' 
fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL (v5.1)

See merge request espressif/esp-idf!35946
 2024-12-26 10:48:58 +08:00
Song Ruo Jing
9026c0905e fix(clk): add an inevitable kconfig option to be selected to use rc32k 2024-12-25 20:08:56 +08:00
Song Ruo Jing
6a26acf647 fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL 
Align C6/H2 rtc_clk_cpu_freq_set_xtal behavior to other chips
 2024-12-24 22:33:38 +08:00
wanckl
67cb6b21c1 fix(pmu): c61 and h2 update pmu_icg_mapping.h 2024-12-24 16:10:27 +08:00
Li Shuai
2b406b6810 fix(esp_hw_support): fix the issue of regdma wait node to immediately return to done 2024-12-03 10:35:06 +08:00
Song Ruo Jing
c2138be7ee feat(soc): support SOC_GPIO_IN_RANGE_MAX/SOC_GPIO_OUT_RANGE_MAX 2024-11-18 14:13:29 +08:00
Chen Jichang
10ad141972 fix(parlio): fix spelling error in reg_base.h 2024-11-07 14:59:26 +08:00
C.S.M
5b43155723 fix(usb_serial_jtag): Fix issue that use u32_reg read/write cannot be used to modify fifo regs 2024-10-18 16:07:00 +08:00
Song Ruo Jing
c57bfa3737 fix(gpio_etm): allow one GPIO binds to multiple ETM tasks 2024-04-24 17:10:03 +08:00
Cao Sen Miao
9025e440ae fix(temperature_sensor): Cannot switch the range smmothly on esp32h2 2024-02-28 12:39:07 +08:00
morris
92b25c06b3 Merge branch 'bugfix/fix_incorrect_regbase_name_of_i2s_v5.1' into 'release/v5.1' 
fix(i2s): fixed incorrect reg base name on C3 (v5.1)

See merge request espressif/esp-idf!28630
 2024-02-28 11:41:58 +08:00
Aditya Patwardhan
55c5c8367b Merge branch 'bugfix/soc_cpu_subsys_region_v5.1' into 'release/v5.1' 
fix(soc): change debug addr range to CPU subsystem range (v5.1)

See merge request espressif/esp-idf!28672
 2024-02-28 11:16:48 +08:00
Jiang Jiang Jian
c404e951e3 Merge branch 'docs/rf_coexistence_api_guides_support_esp32c2_v5.1' into 'release/v5.1' 
Docs: RF coexistence api guides support esp32c2 (v5.1)

See merge request espressif/esp-idf!29214
 2024-02-28 11:09:29 +08:00
linruihao
89881c7c59 fix(esp_coex): add support_coexistence soc_caps for esp32c2 and esp32h2 2024-02-23 16:26:10 +08:00
Marius Vikhammer
d9a6158700 fix(system): update reset reasons for C6 and H2 2024-02-22 12:36:09 +08:00
KonstantinKondrashov
f7a920685a feat(efuse): Adds new efuse for esp32h2 2024-01-26 11:39:16 +08:00
Mahavir Jain
614ad494f6 fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-24 12:52:27 +05:30
laokaiyao
d7b6ebe7df fix(i2s): fixed incorrect reg base name on C3 
Closes https://github.com/espressif/esp-idf/issues/12643
 2024-01-23 12:05:45 +08:00
Roshan Bangar
dc9d9b41f2 fix(nimble): Added periodic_adv_enh soc_caps for c2, h2 2023-12-27 15:03:17 +05:30
Xu Si Yu
866bc77246 feat(ieee802154): add tx/rx report for IEEE802.15.4 debug 2023-12-21 15:17:54 +08:00
Jiang Jiang Jian
487adc09f4 Merge branch 'change/change_regdma_power_issue_macro_v5.1' into 'release/v5.1' 
change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG (backport v5.1)

See merge request espressif/esp-idf!27991
 2023-12-21 11:27:10 +08:00
Marius Vikhammer
40bea117e4 Merge branch 'bugfix/s3_irom_addr_v5.1' into 'release/v5.1' 
soc: fix SOC_IROM_MASK_HIGH for esp32s3 (v5.1)

See merge request espressif/esp-idf!27136
 2023-12-20 10:00:39 +08:00
Lou Tianhao
1419db4b91 change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG 2023-12-19 11:44:23 +08:00
morris
eb7022dd06 Merge branch 'contrib/github_pr_12559_v5.1' into 'release/v5.1' 
fix(spi): Correct REG_SPI_BASE(i) macro for all targets (GitHub PR) (v5.1)

See merge request espressif/esp-idf!27714
 2023-12-14 11:08:03 +08:00
Mahavir Jain
ca02c6d274 Merge branch 'fix/rng_register_prefix_discrepency_newer_targets_v5.1' into 'release/v5.1' 
Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2 (v5.1)

See merge request espressif/esp-idf!27684
 2023-12-08 12:01:36 +08:00
harshal.patil
6a990a37ce fix(soc/esp32h2): Fix llperi_rng_data field discrepancy 2023-12-07 11:42:00 +05:30
gaoxu
6190b3f7c9 fix(adc): restore cali registers after light sleep wake up on H2 and enable test 2023-12-06 10:19:52 +00:00
wanlei
3486cf1b60 fix(spi): correct some signals and dummy bits docs 2023-12-06 16:15:23 +08:00
TD-er
8e0d64e94c fix(spi): Correct REG_SPI_BASE(i) macro for all targets 
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
 2023-12-06 16:13:01 +08:00
Shu Chen
ecbbd3c3d9 Merge branch 'backport/add_ot_radio_stats_enable_config_5_1' into 'release/v5.1' 
feat(openthread): backport some openthread features(BackportV5.1)

See merge request espressif/esp-idf!26885
 2023-11-22 12:23:53 +08:00
Mahavir Jain
0ccfa4b0c2 fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose 
In ESP32-H2, the ECDSA peripheral by default uses the TRNG (hardware)
generated k value but it can be overridden to software supplied k.
This can happen through by overriding the `ECDSA_SOFTWARE_SET_K` bit
in the configuration register. Even though the HAL API is not exposed
for this but still it could be achieved by direct register
programming. And for this scenario, if sufficiently random k is not
supplied by the software then it could posses a security risk.

In this change, we are unconditionally programming the efuse
`ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K` bit during startup security
checks itself. Additionally, same is ensured in the `esp_efuse_write_key`
API as well. This always enforces the hardware k mode in the ECDSA
peripheral and ensures strongest possible security.
 2023-11-20 16:03:29 +05:30
Jiang Jiang Jian
5719d882d1 Merge branch 'bugfix/fix_onebyte_watchpoint_setting_v5.1' into 'release/v5.1' 
fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting (v5.1)

See merge request espressif/esp-idf!27215
 2023-11-20 17:37:03 +08:00
morris
1b3713f7cd Merge branch 'feature/support_adc_calibration_on_h2_v5.1' into 'release/v5.1' 
adc_cali: supported adc calibration v1 on ESP32H2 (v5.1)

See merge request espressif/esp-idf!26963
 2023-11-17 16:41:00 +08:00
morris
ddb6d22468 Merge branch 'feature/gpio_dump_io_info_v5.1' into 'release/v5.1' 
feat(gpio): add a dump API to dump IO configurations (v5.1)

See merge request espressif/esp-idf!26870
 2023-11-17 16:30:22 +08:00
wuzhenghui
eb45eec5db change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 20:40:03 +08:00
Ivan Grokhotkov
c43b66cd35 fix(soc): update SOC_IROM_MASK_HIGH for esp32, c6, h2 for consistency 2023-11-14 14:27:24 +01:00