alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-22 09:06:27 +00:00
Code Issues Packages Projects Releases Wiki Activity
33,454 Commits 21 Branches 168 Tags
a4bfa19ebd21f012648c268f5db95a0111f7cee6
Commit Graph

17 Commits

Author SHA1 Message Date
TD-er
a4bfa19ebd fix(spi): Correct REG_SPI_BASE(i) macro for all targets 
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
 2023-12-06 14:44:26 +08:00
wuzhenghui
2b600df4ee fix(esp_pm): Constrains the minimum frequency of APB_MAX when the modem is working 2023-07-14 20:10:16 +08:00
Song Ruo Jing
2c2a62e323 clk_tree: Add basic clock support for esp32h2 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration

Remove FPGA build for esp32h2
 2023-02-20 17:15:02 +08:00
Omar Chebib
53c7dd4efc WDT: implement interrupt wdt and task wdt for ESP32-C2 
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
 2022-09-15 14:37:59 +08:00
wuzhenghui
7cb9304b65 Clean IRAM and DRAM address space conversion macros 2022-07-29 17:07:39 +08:00
songruojing
b3d8db3ae2 bootloader, esp_system: esp32c2 console uart to support 26MHz xtal 
Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h
 2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
3973db7664 soc: make register access macros compatible with C++20 
In C++20, using the result of an assignment to a 'volatile' value is
deprecated.

Breaking change: register "setter" or modification macros can no
longer be used as expressions.

Closes https://github.com/espressif/esp-idf/issues/9170
 2022-06-17 18:09:22 +02:00
morris
f7c9b8fd58 soc: remove dport register assert for esp32s2 
Closes https://github.com/espressif/esp-idf/issues/8176
 2022-01-06 23:10:22 +08:00
morris
24acdf23ee soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
Konstantin Kondrashov
4972605b16 esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt 2021-08-03 14:35:29 +08:00
Darian Leung
1fabfd005b soc: Fix SOC_IROM_MASK_HIGH address 
The high address limit IROM on the esp32s2 is incorrect, thus
causing backtrace printing to think valid function PCs are invalid.
 2021-01-25 14:54:25 +08:00
Angus Gratton
420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00
Renz Bagaporo
79887fdc6c soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
Renz Christian Bagaporo
1f2e2fe8af soc: separate abstraction, description and implementation 2020-02-11 14:30:42 +05:00
Andrei Gramakov
4e8b4b9e49 soc: add USB peripheral register definitions, hal level, reg map, etc 2020-02-10 08:33:39 +00:00
Konstantin Kondrashov
739eb05bb9 esp32: add implementation of esp_timer based on TG0 LAC timer 
Closes: IDF-979
 2020-02-06 14:00:18 +08:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00