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174 Commits

Author SHA1 Message Date
Jiang Jiang Jian
fed7e38609 Merge branch 'fix/esp32p4_lightsleep_fixes_v5.3' into 'release/v5.3' 
fix(esp_hw_support): some fixes of esp32p4 lightsleep retention & power switch process (v5.3)

See merge request espressif/esp-idf!37097
 2025-02-21 11:03:20 +08:00
wuzhenghui
1f6d8d4e5d fix(esp_hw_support): fix esp32s2/esp32s3 RTC IOMUX clock management 2025-02-20 19:39:02 +08:00
Song Ruo Jing
5ed33be402 fix(pmu): enable all func clock icg during retention 
This should only increase a tiny amount of the power consumption in the retention process,
but save debug time since some module register read/write relies not only APB but also func clock.
 2025-02-20 15:04:13 +08:00
Jiang Jiang Jian
ec02fb249e Merge branch 'feat/wait_pll_stable_after_sleep_wakeup_fix_xtal_v5.3' into 'release/v5.3' 
feat(esp_hw_support): wait pll stable after sleep wakeup (v5.3)

See merge request espressif/esp-idf!36019
 2025-02-20 11:22:18 +08:00
wuzhenghui
cbd3df38d9 fix(esp_hw_support): fix lp/hp clock wait time calculation 2025-02-17 21:49:26 +08:00
wuzhenghui
812a609eca change(esp_hw_support): wait pll calibration done in regdma link instead of wait fixed value 2025-02-17 19:13:17 +08:00
wuzhenghui
0e2335f6f9 fix(esp_hw_support): add timer wakeup sleep duration check 
Closes https://github.com/espressif/esp-idf/issues/15255
 2025-02-17 19:09:44 +08:00
Michael (XIAO Xufeng)
4c422b18ff Merge branch 'bugfix/warn_rc32k_use_in_kconfig_v5.3' into 'release/v5.3' 
fix(clk): add an inevitable kconfig option to be selected to use rc32k (v5.3)

See merge request espressif/esp-idf!35965
 2025-01-07 15:50:42 +08:00
Marius Vikhammer
4531d056e9 fix(interrupt): fixed wrongly reserved interrupt for wifi on H2 2025-01-02 16:44:05 +08:00
Song Ruo Jing
a2178b0fa2 fix(clk): add an inevitable kconfig option to be selected to use rc32k 2024-12-25 20:01:37 +08:00
Song Ruo Jing
c73be9a62d fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL 
Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips
 2024-12-24 22:08:46 +08:00
hongshuqing
24bdc5312d fix: fix pll low temp bug 2024-11-14 18:58:28 +08:00
Jiang Jiang Jian
b840737ebf Merge branch 'fix/fix_ota_slowclock_switching_v5.3' into 'release/v5.3' 
fix(esp_hw_support): fix rtc slow clock missing after the OTA app changes the slow clock source (v5.3)

See merge request espressif/esp-idf!34474
 2024-11-08 16:34:22 +08:00
Jiang Jiang Jian
7229ec4be9 Merge branch 'feature/check_efuse_blk_after_ota_v5.3' into 'release/v5.3' 
feat(bootloader): support to check efuse block revision (v5.3)

See merge request espressif/esp-idf!33136
 2024-10-28 12:20:05 +08:00
wuzhenghui
2153a6b81e fix(esp_hw_support): enable all supported slow clock at pmu_init 2024-10-28 12:14:54 +08:00
hongshuqing
5c2c1d8a24 fix(h2): modify wrong lslp drvb config 2024-10-18 17:01:00 +08:00
Jiang Jiang Jian
ef53542940 Merge branch 'fix/fix_clock_retention_link_context_v5.3' into 'release/v5.3' 
fix(esp_hw_support): add clock retention contents for esp32c6 & esp32h2  (v5.3)

See merge request espressif/esp-idf!33608
 2024-09-27 12:18:11 +08:00
wuzhenghui
234103d7aa fix(esp_hw_support): add clock retention contents 2024-09-18 17:22:21 +08:00
Song Ruo Jing
a9fcf0d57a fix(clk): warn the users to avoid using RC32K clock 2024-09-13 11:44:51 +08:00
laokaiyao
1ece052ce3 feat(bootloader): support to check efuse block revision 
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
 2024-08-28 12:12:00 +08:00
Xiao Xufeng
f81cece9d4 fix(startup): move rtc initialization before MSPI timing tuning to improve stability 2024-08-05 00:35:10 +08:00
wuzhenghui
dd5a5f1cf2 feat(esp_hw_support): support DCDC always on 2024-06-24 11:48:23 +08:00
Jiang Jiang Jian
a31806d076 Merge branch 'feature/esp32c6_pu8m_in_sleep_support_v5.3' into 'release/v5.3' 
feat(sleep): support 8m force pu in sleep for esp32c6 & esp32h2 (v5.3)

See merge request espressif/esp-idf!30999
 2024-06-11 10:48:05 +08:00
wuzhenghui
091da3d631 fix(esp_driver_gpio): manage lp_io module clock by driver 
Closes https://github.com/espressif/esp-idf/issues/13683
 2024-06-06 19:27:57 +08:00
chaijie@espressif.com
b8d9da5c03 feat(sleep): support 8m force pu in sleep for esp32c6/esp32h2 2024-05-22 11:35:00 +08:00
Jiang Jiang Jian
9081d54aa7 Merge branch 'fix/fix_pmu_power_domain_initialize_order' into 'master' 
fix(esp_hw_support): fix pmu power domain initialize order

See merge request espressif/esp-idf!30095
 2024-04-10 17:23:47 +08:00
morris
e8b6d2280d change(gptimer): use private unsafe RCC LL functions in bootloader 2024-04-08 17:48:20 +08:00
wuzhenghui
24244f04f2 fix(esp_hw_support): fix pmu power domain initialize order 2024-04-08 15:47:59 +08:00
Laukik Hase
48503dd39f fix(esp_hw_support): Fix the flash I/DROM region PMP protection 2024-04-02 18:41:07 +05:30
Li Shuai
262be04b21 change(esp_hw_support): modify system and modem clock to support modem domain power down 2024-03-29 16:13:52 +08:00
wuzhenghui
194c38479e refactor(esp_hw_support): split pd_top clock retention initialization by target 2024-03-28 19:18:24 +08:00
Omar Chebib
a79c6f7f67 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-03-27 16:21:25 +08:00
Wu Zheng Hui
5a682c3bbb Merge branch 'feature/optimize_chips_active_power' into 'master' 
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
 2024-03-14 12:08:33 +08:00
Jiang Jiang Jian
6a879bf2d2 Merge branch 'bugfix/fix_maximum_value_of_config_rtc_clk_cal_cycles_bug' into 'master' 
ESP All Chip: fixed the maximum value of config RTC_CLK_CAL_SYCLES bug

See merge request espressif/esp-idf!29423
 2024-03-14 10:44:17 +08:00
wuzhenghui
129bfce02e feat(esp_hw_support): support esp32p4 pll start/stop event callback 2024-03-10 10:51:28 +08:00
wuzhenghui
856f043331 feat(esp_hw_support): add esp32p4 pmu initial support 2024-03-10 10:51:28 +08:00
wuzhenghui
f5707c6ab8 feat(system): gate the REF_TICK clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
Omar Chebib
eeb5e2f080 Merge branch 'refactor/cpu_interrupt_table' into 'master' 
refactor(Core System/Interrupts): changed reserved interrupt functions to be now defined per SoC

Closes IDF-5728

See merge request espressif/esp-idf!29020
 2024-03-06 11:26:17 +08:00
hongshuqing
d78805670a fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug 2024-03-05 19:33:30 +08:00
Omar Chebib
c1849df791 refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC 2024-02-28 15:21:10 +08:00
Laukik Hase
366e4ee944 refactor(esp_hw_support): Remove redundant PMP entry for ROM region 
- The ROM text and data sections share the address range
    (see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
  - Initially, we had two PMP entries for this address range - one marking the
    region as RX and the other as R.
  - However, the latter entry is redundant as the former locks the PMP settings.
  - We can divide the ROM region into text and data sections later when we
    define boundaries marking these regions from the ROM.
 2024-02-28 10:54:38 +05:30
Laukik Hase
ff839be31d fix(esp_hw_support): Fix the I/DCACHE region PMP protection 2024-02-28 10:54:37 +05:30
Song Ruo Jing
dce27c3b09 change(clk_tree): add LP_DYN_FAST_CLK to soc_module_clk_t 2024-02-07 14:37:48 +08:00
wuzhenghui
0c2f811ca8 feat(esp_hw_support): support gdma register context sleep retention 2024-02-02 11:21:40 +08:00
Michael (XIAO Xufeng)
6dbb3059f9 Merge branch 'h2_auto_dbias_master_hsq' into 'master' 
ESP32H2: Active & sleep dbias get from efuse to fix the voltage

See merge request espressif/esp-idf!27483
 2024-01-29 10:16:15 +08:00
Song Ruo Jing
cf93777077 refactor(rtc): move soc/rtc.h from soc to esp_hw_support component 
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
 2024-01-25 19:15:33 +08:00
hongshuqing
0b79d9bf4c feat(pmu): set fix voltage to different mode for esp32h2 
h2 remove include
 2024-01-24 13:11:41 +08:00
Mahavir Jain
e3d4b901f9 Merge branch 'bugfix/compilation_failed_in_bootloader_with_sb_fe_verbose' into 'master' 
fix(bootloader): Fix compilation issue in bootloader build during verbose+sb+fe

Closes IDF-6373

See merge request espressif/esp-idf!26339
 2024-01-23 13:29:02 +08:00
Mahavir Jain
9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-22 13:34:32 +08:00
nilesh.kale
59c5b5fe6b fix(bootloader): Fix compilation issue in bootloader build during verbose+sb+fe 2024-01-18 12:15:15 +05:30