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118 Commits

Author SHA1 Message Date
Jiang Jiang Jian
fed7e38609 Merge branch 'fix/esp32p4_lightsleep_fixes_v5.3' into 'release/v5.3' 
fix(esp_hw_support): some fixes of esp32p4 lightsleep retention & power switch process (v5.3)

See merge request espressif/esp-idf!37097
 2025-02-21 11:03:20 +08:00
Song Ruo Jing
5ed33be402 fix(pmu): enable all func clock icg during retention 
This should only increase a tiny amount of the power consumption in the retention process,
but save debug time since some module register read/write relies not only APB but also func clock.
 2025-02-20 15:04:13 +08:00
Jiang Jiang Jian
ec02fb249e Merge branch 'feat/wait_pll_stable_after_sleep_wakeup_fix_xtal_v5.3' into 'release/v5.3' 
feat(esp_hw_support): wait pll stable after sleep wakeup (v5.3)

See merge request espressif/esp-idf!36019
 2025-02-20 11:22:18 +08:00
wuzhenghui
7147d7b366 change(esp_hw_support): wrapper sleep dcdc/ldo ops with ll 2025-02-19 21:37:38 +08:00
wuzhenghui
2445545a17 fix(esp_hw_support): fix DCDC switch bad software powerdown 2025-02-19 21:36:40 +08:00
wuzhenghui
08e7ef62da change(esp_hw_support): define Cache invalidate in sleep process to avoid dirtying the L1 Cache 2025-02-19 21:36:13 +08:00
wuzhenghui
cbd3df38d9 fix(esp_hw_support): fix lp/hp clock wait time calculation 2025-02-17 21:49:26 +08:00
wuzhenghui
812a609eca change(esp_hw_support): wait pll calibration done in regdma link instead of wait fixed value 2025-02-17 19:13:17 +08:00
wuzhenghui
0e2335f6f9 fix(esp_hw_support): add timer wakeup sleep duration check 
Closes https://github.com/espressif/esp-idf/issues/15255
 2025-02-17 19:09:44 +08:00
Jiang Jiang Jian
4e0cb9a140 Merge branch 'fix/fix_p4_deepsleep_io_leakage_v5.3' into 'release/v5.3' 
fix(esp_hw_support): fix esp32p4 JTAG pad deepsleep current leakage (v5.3)

See merge request espressif/esp-idf!36009
 2025-01-17 12:10:46 +08:00
Michael (XIAO Xufeng)
4c422b18ff Merge branch 'bugfix/warn_rc32k_use_in_kconfig_v5.3' into 'release/v5.3' 
fix(clk): add an inevitable kconfig option to be selected to use rc32k (v5.3)

See merge request espressif/esp-idf!35965
 2025-01-07 15:50:42 +08:00
wuzhenghui
a18fe20e9b fix(esp_hw_support): fix esp32p4 JTAG pad deepsleep current leakage 2024-12-26 16:05:14 +08:00
Song Ruo Jing
a2178b0fa2 fix(clk): add an inevitable kconfig option to be selected to use rc32k 2024-12-25 20:01:37 +08:00
Song Ruo Jing
c73be9a62d fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL 
Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips
 2024-12-24 22:08:46 +08:00
morris
6f992acf31 feat(mipi): fine tune DPHY PLL clock 2024-11-29 10:04:38 +08:00
Jiang Jiang Jian
6b2ac26da3 Merge branch 'feature/support_apll_on_p4_v5.3' into 'release/v5.3' 
feat(clock): support apll clock on p4 (v5.3)

See merge request espressif/esp-idf!33214
 2024-11-14 18:54:59 +08:00
Michael (XIAO Xufeng)
f7154edfd8 Merge branch 'feat/support_bod_p4_eco2_v5.3' into 'release/v5.3' 
feat(bod): Update bod threshold on esp32p4-eco2 (backport v5.3)

See merge request espressif/esp-idf!34591
 2024-11-07 21:36:01 +08:00
C.S.M
4049f2b5fb feat(bod): Update bod threshold on esp32p4-eco2 2024-11-01 15:31:02 +08:00
wuzhenghui
655a99bec8 fix(esp_hw_support): fix writeback cache to psram after vo2 powerdown 2024-11-01 14:14:35 +08:00
laokaiyao
5b03fff32e feat(clock): support apll clock on p4 2024-10-31 11:01:04 +08:00
Jiang Jiang Jian
7229ec4be9 Merge branch 'feature/check_efuse_blk_after_ota_v5.3' into 'release/v5.3' 
feat(bootloader): support to check efuse block revision (v5.3)

See merge request espressif/esp-idf!33136
 2024-10-28 12:20:05 +08:00
wuzhenghui
855bba0582 feat(esp_hw_support): support power down PSRAM or Flash during sleep for esp32p4 v1.0 2024-10-23 16:03:39 +08:00
Jiang Jiang Jian
d11c994692 Merge branch 'bugfix/fix_wrong_sleep_memory_param_p4_c5_c61_to_v5.3' into 'release/v5.3' 
fix(sleep): fix_wrong_sleep_param_for_lp_memory_retention (v5.3)

See merge request espressif/esp-idf!33422
 2024-10-14 10:22:28 +08:00
wuzhenghui
a70fe8bdee change(esp_hw_support): switch hp_sys default power mode with clock src selection 2024-10-11 16:06:10 +08:00
chaijie@espressif.com
3497691fc5 fix(sleep): fix_wrong_sleep_param_for_lp_memory_retention (v5.3) 2024-09-29 10:30:00 +08:00
wuzhenghui
a82938bb7e fix(esp_hw_support): fix esp32p4 CPU frequency switching timing 2024-09-27 17:29:54 +08:00
wuzhenghui
5b1796b284 revert(esp_hw_support): revert stall another core during cpu/mem/apb freq switching 
This reverts commit 4c2b86f5.
 2024-09-27 17:28:05 +08:00
harshal.patil
e4de9ffe7d fix(cpu_region_protect): Reset PMA entries before using them 
- ROM uses some PMA entries so we clear such PMA entries before using them in ESP-IDF
 2024-09-24 16:56:17 +05:30
Song Ruo Jing
a9fcf0d57a fix(clk): warn the users to avoid using RC32K clock 2024-09-13 11:44:51 +08:00
wuzhenghui
21d430cf28 fix(esp_hw_support): always writeback L1D$ before sleep to keep cpu/regdma data consistency 2024-09-04 16:42:54 +08:00
wuzhenghui
2c68d03182 feat(esp_hw_support): support esp32p4 psram retention 2024-09-04 16:41:35 +08:00
wuzhenghui
7cc55a0e0b fix(esp_hw_support): fix bad power parameter if PSRAM is enabled during sleep 2024-09-04 16:41:34 +08:00
laokaiyao
1ece052ce3 feat(bootloader): support to check efuse block revision 
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
 2024-08-28 12:12:00 +08:00
morris
479c835d1a feat(ldo): add config to let hardware control the ldo output 
If LDO1 is used by spi flash, then we recommend to give the ownership to
the hardware. Software just read the parameters from the efuse and set
to PMU.
 2024-08-14 10:25:04 +08:00
Jiang Jiang Jian
e0991facf5 Merge branch 'bugfix/fix_esp32p4_deepsleep_gpio_wakeup_support_v5.3' into 'release/v5.3' 
feat(esp_hw_support): support esp32p4 gpio/ext1 wakeup deepsleep (v5.3)

See merge request espressif/esp-idf!32164
 2024-07-17 11:03:25 +08:00
wuzhenghui
603ad059a3 fix(esp_hw_support): hold LP_IO mode if LP_PERI domain powerdown in sleep 2024-07-16 22:00:40 +08:00
wuzhenghui
4c2b86f5fe fix(esp_hw_support): stall another core during cpu/mem/apb freq switching 2024-07-16 21:47:04 +08:00
Jiang Jiang Jian
5c180bf3b6 Merge branch 'feat/esp32p4eco_sleep_feature_update_v5.3' into 'release/v5.3' 
feat(esp_hw_support): esp32p4eco1 sleep feature update (v5.3)

See merge request espressif/esp-idf!31682
 2024-07-15 19:35:56 +08:00
wuzhenghui
edf14a1de1 fix(esp_hw_support): disable mpll clock after L1 dcache writeback 2024-07-11 13:59:42 +08:00
Michael (XIAO Xufeng)
33c3d327c5 Merge branch 'feat/esp32p4_default_rev_0.1_v5.3' into 'release/v5.3' 
feat(esp32p4): make revision v0.1 the default version (v5.3)

See merge request espressif/esp-idf!31601
 2024-07-05 10:52:02 +08:00
wuzhenghui
0291269573 fix(esp_hw_support): wait eFuse controller idle after sleep wakeup 2024-06-28 13:58:44 +08:00
Xiao Xufeng
3105644642 feat(esp32p4): make revision v0.1 the default version 2024-06-24 20:11:02 +08:00
wuzhenghui
dd5a5f1cf2 feat(esp_hw_support): support DCDC always on 2024-06-24 11:48:23 +08:00
wuzhenghui
79c48b4707 feat(esp_pm): add DCDC always on config 2024-06-24 11:48:18 +08:00
wuzhenghui
2ab144dc3a fix(esp_hw_support): set pau entry backup configuration with link update 2024-06-13 14:08:37 +08:00
morris
10f8cc42fb Merge branch 'esp32p4/add_adc_support_v5.3' into 'release/v5.3' 
feat(adc): support ADC oneshot/continuous mode on ESP32P4(v5.3)

See merge request espressif/esp-idf!31367
 2024-06-13 11:00:59 +08:00
Aditya Patwardhan
e819b8c0b9 Merge branch 'fix/incorrect_pma_config_esp32p4_v5.3' into 'release/v5.3' 
fix(esp_hw_support): Fix incorrect PMA configuration for ESP32-P4 (v5.3)

See merge request espressif/esp-idf!31431
 2024-06-13 00:06:26 +08:00
gaoxu
3f5037866b fix(dma): feat(adc): support ADC oneshot mod on ESP32P4 2024-06-12 18:16:41 +08:00
harshal.patil
0868604664 fix(esp_hw_support): Fix incorrect PMA configuration for ESP32-P4 
- As the PMA entry that made some memory regions cacheable was
assigned the highest priority, some intermediate inaccessible
memory regions bypassed protection.

- Added tests for the same

- Verified that even after changing the priority of the PMA entry,
a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address)
still needs the same number (29) of CPU cycles.
 2024-06-11 12:23:06 +05:30
Armando
05f44bddf0 feat(isp): added isp dvp driver 2024-06-11 10:18:16 +08:00