Commit Graph

20 Commits

Author SHA1 Message Date
wanlei
b81cafe42e refac(spi): update periph_module_xxx with rcc_automic_lock for periph bus 2023-10-17 11:32:23 +08:00
wanlei
00fcdce725 feat(spi_master): p4 add master driver supported 2023-10-08 14:45:12 +08:00
Planck (Lu Zeyu)
255d499884 fix(ll): fix cpp compile error
Merges https://github.com/espressif/esp-idf/pull/12093

fix(ll): remove FLAG_ATTR macro

Such kind of operator overload will not work because C++ thinks such overload is ambiguous and it still prefer the built-in one which accepts and returns integer. Manually force type conversion seems to be unavoidable.
2023-09-14 14:48:12 +08:00
wanlei
8f5851d064 fix(all): unify default mosi level to low on all targets 2023-07-24 15:45:21 +08:00
Armando
ea10aac4f0 spi: added transaction length check to refuse longer than hardware supported length 2023-05-04 11:37:23 +08:00
wanlei
184145817c spi_master: add feature spi periph clk source selectable 2023-01-18 15:40:12 +08:00
gaoxu
3610b14aef SPI : fix wrong dummy cycle on quad mode and put get-command function in spi_ll.h
1.The dummy_bits is set to 4 in ESP32C3/C2, therefore, the data transmission started too early.This commit fix this issue by changing dummy_bits to 8.
2.Put the spi command the spi defintion in spi_types.h
3.Put the function which get spi command or dummy bits in spi_ll.h
2022-08-23 10:46:56 +08:00
morris
2c7cfdd784 spi: define tranfer max bit length in LL 2022-03-10 13:40:43 +08:00
Armando
56a707eef4 spi_master: fix spi cs_ena_posttrans issue 2022-01-06 17:54:58 +08:00
SalimTerryLi
874a720286 soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
2021-08-30 13:50:58 +08:00
morris
71d475149d lcd: update doc unit test and example to support 8-line spi 2021-08-19 16:40:22 +08:00
bizhuangyang
8143832041 spi_master:support octal mode for esp32s2 and esp32s3
Add support for 8-line spi for lcd on esp32s2 and esp32s3

Closes https://github.com/espressif/esp-idf/issues/6371
2021-08-19 16:40:22 +08:00
Omar Chebib
a6e14c37b2 SPI: chip select can now be kept active if the bus has been acquired
The user can now request the chip select to remain active after the current
transfer. In order to do so, he MUST acquire the bus first with `spi_device_acquire_bus()`
function, else, an error is returned.
2021-07-21 10:39:45 +08:00
Gustavo Henrique Nihei
4bc9e18124 spi: Ensure DMA In-Link EOF is generated by trans_done on SPI Slave 2021-06-28 18:58:59 -03:00
Gustavo Henrique Nihei
fb8d9f76b3 spi: Remove Slave TX/RX set bitlen not effective for ESP32-S2/C3/S3
Furthermore, RX_EOF_EN should only be set when SPI Slave is configured
for segment transfer mode and the "ms_data_bitlen" field is configured
to control the "IN_SUC_EOF" interrupt. Since "ms_data_bitlen" is not
set anymore for S2, C3 and S3, "RX_EOF_EN" should be cleared.
2021-06-28 18:58:59 -03:00
morris
9afdf54748 hal: added HAL_ASSERT 2021-06-22 11:28:01 +08:00
Gustavo Henrique Nihei
c1b3d77dcf spi: Fix wrong target register for interrupt disable 2021-05-31 11:25:32 -03:00
Armando
831b6127d7 spi: update interrupt set in spi_ll.h 2021-04-27 11:11:00 +08:00
Armando
0538dc2d93 spi_slave_hd: add DMA Append Mode feature 2021-01-21 18:53:53 +08:00
Angus Gratton
7c08be5771 hal: Add initial ESP32-C3 support
From internal commit 7761d6e8
2020-11-30 15:23:15 +11:00