morris
e121a77c92
fix(dma): also consider buffer alignment when calculating the DMA nodes
...
Closes https://github.com/espressif/esp-idf/issues/15228
2025-02-11 13:46:12 +08:00
morris
5c0611cb3b
feat(async_memcpy): support rx buffer unaligned to cache line size
2025-02-11 13:46:12 +08:00
morris
3e3f82a3fd
refactor(async_memcpy): clean up memory allocation code
2024-05-30 18:26:34 +08:00
morris
dc060460ea
change(async_memcpy): set DMA transfer burst size
2024-05-24 22:43:55 +08:00
morris
28db901d77
fix(mcp): align the descriptor to cache line size for DMA memory copy
2024-01-09 10:12:36 +08:00
morris
987174c203
feat(async_mcp): access DMA descriptor bypass cache
2023-12-10 15:19:27 +08:00
Armando
ec27891af6
change(cache): swap cache hal arg 'type' and 'level'
2023-09-22 14:19:41 +08:00
Armando
cc581c3c36
change(cp_dma): check cache line by cache level
2023-09-22 14:19:41 +08:00
morris
6bb05cccdd
feat(rmt): add driver support for esp32p4
...
including DMA feature
2023-09-19 12:54:14 +08:00
morris
595c3fe6a2
fix(async_memcpy): destination alignment check against cache line size
...
On ESP32P4, becasue we need to invalidate the destination buffer,
if the buffer is not aligned to cache line, then it might break
other date structure, randomly.
2023-08-15 17:40:17 +08:00
morris
fd3d1aa101
feat(async_memcpy): refactor driver code to support different DMA backen
...
To support AHB and AXI DMA memory copy for the same target (esp32p4).
2023-08-03 12:02:09 +08:00
