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1083 Commits

Author SHA1 Message Date
Jiang Jiang Jian
b259c45528 Merge branch 'esp32p4_fix_bootloader_flash_read_allow_decrypt_v5.5' into 'release/v5.5' 
fix(bootloader_flash): always invalidate FLASH_READ_VADDR before read (v5.5)

See merge request espressif/esp-idf!43957
 2025-12-30 10:33:27 +08:00
Mahavir Jain
f8fe1ce0ea Merge branch 'fix/secure_boot_verify_app_api_support_ecdsa_p384_v5.5' into 'release/v5.5' 
Application's Secure Boot verify API support ECDSA-P384 (v5.5)

See merge request espressif/esp-idf!44181
 2025-12-29 13:53:00 +05:30
Mahavir Jain
0f474752c7 Merge branch 'fix/fix_bootloader_skip_validate_in_deep_sleep_v5.5' into 'release/v5.5' 
fix(bootloader): fix signature verification skip in deep sleep scenarios (v5.5)

See merge request espressif/esp-idf!43696
 2025-12-26 09:53:51 +05:30
harshal.patil
cb9acbdd21 fix(secure_boot): Application's Secure Boot verify API support ECDSA-P384 2025-12-24 10:42:15 +05:30
Jiang Jiang Jian
ddb9f5d9dc Merge branch 'fix/fix_mspi_write_stuck_after_reset_v5.5' into 'release/v5.5' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 (v5.5)

See merge request espressif/esp-idf!43732
 2025-12-04 10:34:56 +08:00
Samuel Obuch
3d2dda8e72 fix(bootloader_flash): invalidate FLASH_READ_VADDR before read 
Fixed address to match corresponding mmu_hal_map_region call.
FLASH_MMAP_VADDR was invalidated by mistake in commit
ea38a2e9a4
 2025-12-03 10:00:57 +01:00
wuzhenghui
104145de7f fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 2025-12-02 13:34:17 +08:00
gaoxu
dfef29c007 feat(rng): support P4 ECO5 TRNG 2025-12-01 15:31:44 +08:00
gaoxu
94679d0b0e refactor(rng): refactor to use hal/ll apis for P4 2025-12-01 15:31:44 +08:00
Mahavir Jain
ac8b73bda1 fix(bootloader): fix signature verification skip in deep sleep scenario 
For CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP enabled and exit from
deep sleep case the secure boot signature verification must be skipped
to improve the wakeup performance.

Closes https://github.com/espressif/esp-idf/issues/15590
 2025-11-25 10:11:58 +05:30
Song Ruo Jing
fb20e147d5 fix(console): release default console UART pins if console is switched in bootloader 
Also print out console UART pin number in app cpu_startup stage

Closes https://github.com/espressif/esp-idf/issues/16764
Closes https://github.com/espressif/esp-idf/issues/17459
 2025-11-21 22:11:25 +08:00
wuzhenghui
3ee348fe52 fix(esp_hw_support): add p4 rev3.0 MSPI workaround for deepsleep 2025-10-30 19:09:44 +08:00
Laukik Hase
e54ebe08a4 fix(esp_tee): Handle the SPI1 WB mode incompatibility in TEE flash APIs on ESP32-C5 
- When `esp_flash_read()` is invoked from REE, it internally enables WB mode
  via `spi_flash_ll_wb_mode_enable()`. However, the ROM flash APIs used by TEE
  do not support WB mode, resulting in failures when TEE attempts to access
  flash after this call.
- This commit adds a workaround in the TEE flash layer by saving WB mode state,
  temporarily disabling it for ROM API calls, and restoring it afterward.
 2025-10-27 11:17:06 +05:30
morris
695f8e46d6 Merge branch 'fix/make_bootloader_flash_size_correct_v5.5' into 'release/v5.5' 
fix(bootloader_flash): Make bootloader flash size accurate , etc. (backport v5.5)

See merge request espressif/esp-idf!41706
 2025-10-20 14:21:40 +08:00
Mahavir Jain
ea36c4f609 Merge branch 'feature/esp_tee_c5_v5.5' into 'release/v5.5' 
feat(esp_tee): Initial support for ESP32-C5 and related changes (v5.5)

See merge request espressif/esp-idf!42357
 2025-10-16 09:39:23 +05:30
Mahavir Jain
042f29dd66 Merge branch 'fix/change_write_protection_bit_of_shared_security_efuses_v5.5' into 'release/v5.5' 
Reorder write protection bits of some shared security efuses (v5.5)

See merge request espressif/esp-idf!42033
 2025-10-15 09:38:59 +05:30
C.S.M
018d7c5c79 fix(bootloader_flash): Make bootloader flash size accurate 2025-10-14 17:45:29 +08:00
Laukik Hase
73d0dadd6b fix(esp_tee): Correct flash operation bound checks to handle all overlap cases 
- Ensure bound checks correctly handle all scenarios, including
  when a requested operation's (SPI0/1) range fully contains the
  TEE-protected region.
- Disable delegation of INTWDT timeout and Cache error interrupts as they reset
  the device after the panic handler
 2025-10-14 10:12:28 +05:30
armando
e6d4eec507 feat(p4): p4 rev3 real chip support 2025-10-13 15:25:23 +08:00
harshal.patil
175a6510f5 fix(bootloader_support): Allow pre-programmed XTS-AES psuedo round level efuses 
- The API esp_flash_encryption_set_release_mode() by defualt programs
the XTS-AES pseudo round level efuse to level low but did not considered
any existing value that would have been programmed in the efuse bit.
 2025-10-13 10:40:16 +05:30
harshal.patil
70a8b4d842 fix(bootloader_support): Reorder write disabling ECDSA_CURVE_MODE 2025-10-13 10:40:16 +05:30
harshal.patil
d902072d80 fix(bootloader_support): Reorder write protection bits of some shared security efuses 2025-10-13 10:40:16 +05:30
Mahavir Jain
fa08f239c0 Merge branch 'bugfix/encrypt_len_for_sb_update_case_v5.5' into 'release/v5.5' 
fix(bootloader): correct encryption length for secure update without secure boot (v5.5)

See merge request espressif/esp-idf!41923
 2025-09-21 18:37:43 +05:30
Mahavir Jain
b0713ffe08 fix(bootloader): correct encryption length for secure update without secure boot 
For secure update without secure boot case, the encryption length for
app image must consider signature block length as well. This was
correctly handled for secure boot case but not for secure update without
secure boot.
 2025-09-16 10:16:37 +05:30
Marius Vikhammer
590cb66669 ci(system): enabled and cleanup misc system test-apps build-test-rules 2025-08-18 14:22:13 +08:00
harshal.patil
476f8f6f51 feat(bootloader_support): Support Secure Boot using ECDSA-P384 curve 2025-07-25 14:25:31 +05:30
harshal.patil
55f693d4dd change(bootloader_support/secure_boot): Allow NULL as verified_digest for app build 
The esp_secure_boot_verify_sbv2_signature_block() and esp_secure_boot_verify_rsa_signature_block()
APIs need and use the verified_digest argument only for BOOTLOADER_BUILD, but the argument is
not used in the application code, and the value present in verified_digest is considered invalid.
Thus, allow passing NULL as the verified_digest parameter to help some save space.
 2025-07-25 14:23:02 +05:30
harshal.patil
1b3eb8f93e fix(bootloader_support/secure_boot): Fix incorrect usage of ESP_SECURE_BOOT_KEY_DIGEST_LEN 2025-07-25 14:23:02 +05:30
Aditya Patwardhan
a002a04332 feat(soc): Added soc capabilities related to RNG 2025-07-23 18:24:46 +05:30
Jiang Jiang Jian
3c39b32195 Chip/support esp32c61 v5.5 2025-07-22 12:21:36 +08:00
Omar Chebib
20ec15edff fix(esp_system): fix RTC reserved area alignment in the linker script 
Make sure the size of the RTC reserved area complies with the alignment requirement.

Closes https://github.com/espressif/esp-idf/issues/13082
 2025-06-18 20:11:47 +08:00
Aditya Patwardhan
d5323cfaaa Merge branch 'feature/enable_support_for_deterministic_mode_and_ecdsa_192_v5.5' into 'release/v5.5' 
enable support for deterministic mode and ecdsa 192 in ESP32H2 (v5.5)

See merge request espressif/esp-idf!39540
 2025-06-16 18:32:43 +05:30
Aditya Patwardhan
2e7a9174fc Merge branch 'feature/esp_tee_h2_v5.5' into 'release/v5.5' 
feat(esp_tee): Support for ESP32-H2 (v5.5)

See merge request espressif/esp-idf!39311
 2025-06-16 12:04:22 +05:30
nilesh.kale
2d5d7b819f feat: enabled ECDSA-P192 support for ESP32H2 2025-06-16 13:13:03 +08:00
armando
b977a13796 test(psram): re-enable 80M psram tests on C5 ECO2 2025-05-26 11:32:24 +08:00
armando
fafc25b8b9 feat(mspi): supported psram 80MHz timing tuning 2025-05-22 14:42:42 +08:00
Laukik Hase
27496e47f0 feat(esp_tee): Support for ESP32-H2 - the rest of the components 2025-05-21 10:06:17 +05:30
chaijie@espressif.com
45fb5fb793 fix(pmu): fix deepsleep current too big bug for esp32c61 2025-05-20 21:14:33 +08:00
chaijie@espressif.com
63f72f659d feat(power_glich): support power_glitch of esp32c5_eco1 and above, eco32c61 eco2 and above 2025-05-20 21:14:33 +08:00
Mahavir Jain
37e28522c2 fix: secure OTA without secure boot issue for MMU page size configurable SoCs 
For secure app verification during OTA update case, the image was
getting memory mapped twice and hence the failure in verification.

Modified from memory mapped flash read to SPI flash read approach
for the MMU page size from image header.

Regression from 07318a4987

Closes https://github.com/espressif/esp-idf/issues/15936
 2025-05-14 10:53:46 +05:30
Laukik Hase
8a999ea19e fix(security): Set all APM masters to operate in TEE mode by default 2025-05-11 10:01:11 +05:30
Laukik Hase
41bf07e6ce refactor(esp_tee): Remove the deprecated TEE secure storage partition subtype 2025-05-04 18:03:30 +05:30
Armando (Dou Yiwen)
574b27d02c Merge branch 'fix/fix_image_check_16_mega_bytes_limit' into 'master' 
bootloader: fixed image cannot exceed 16MB issue

See merge request espressif/esp-idf!38397
 2025-04-30 10:30:42 +08:00
armando
755fd86b6f fix(bootloader): fixed image cannot exceed 16MB issue 
flash 32-bit-addr is an experimental feature that has multiple
dependencies, e.g. flash chip vendor, etc.

If CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH can be enabled
successfully and tests are passed, we can allow images to be
placed on higher-than-16MB flash addresses
 2025-04-29 15:42:27 +08:00
Mahavir Jain
f3b4050a9f fix: Secure boot (ECDSA) build failure for C6 rev0 target 
Closes https://github.com/espressif/esp-idf/issues/15856
 2025-04-29 12:05:22 +08:00
Mahavir Jain
f7724eedef Merge branch 'feature/enable_secure_boot_for_esp32h21' into 'master' 
feat: enable secure boot support for esp32h21

Closes IDF-11500 and IDF-12161

See merge request espressif/esp-idf!36618
 2025-04-28 11:37:37 +08:00
nilesh.kale
c65858287a feat: enabled secure boot support esp32h21 2025-04-25 17:48:25 +05:30
gaoxu
66bed18464 feat(rng): add regi2c control ref_count 2025-04-25 14:39:12 +08:00
gaoxu
bf335a38f7 fix(adc): fix adc do not enable/disable regi2c registers 2025-04-25 14:39:01 +08:00
Sudeep Mohanty
80910be77a fix(lp-timer): Remove LP Timer interrupt disabling from bootloader 
This commit removes the disabling of the LP Timer interrupt from the
bootloader clock configuration routine. This allows the LP Timer
interrupt to be visible to the LP Core after HP CPU boots up.

Closes https://github.com/espressif/esp-idf/issues/15751
 2025-04-16 16:31:57 +02:00