Starting with ESP32-P4 we can have targets that have more than 1 USB-OTG peripheral.
This commit adds an option to choose which peripherals will be used by USB Host lib.
Internally, we will still have only 1 Root HUB but with multiple Root ports.
- DWC-OTG internal DMA can access psram on esp32p4
- Move DMA memory buffs to psram, to save internal ram
- HCD tests and MSC example runs in CI with psram enabled
Introduce a new HAL API `usb_dwc_hal_set_fifo_config()` that allows advanced users
to manually configure RX, Non-Periodic TX, and Periodic TX FIFO sizes. This offers
fine-grained control beyond the previous bias-based sizing approach.
The HAL function no longer returns `esp_err_t`, and internal validations are enforced
via `HAL_ASSERT()`. Responsibility for input validation has been moved to the HCD layer.
FIFO configuration must be applied before any USB pipes are created or activated.
This feature is intended for use during `usb_host_install()`.
If no custom FIFO configuration is provided (i.e., all values are zero),
the driver falls back to a bias-based default layout based on Kconfig settings
(`CONFIG_USB_HOST_HW_BUFFER_BIAS_*`). Bias resolution is done inside `hcd_port_init()`.
The `port_obj_t` structure has been extended with a `fifo_config` field, which stores
the configuration to allow re-application after a USB port reset.
Obsolete FIFO bias enums (`usb_hal_fifo_bias_t`, `hcd_port_fifo_bias_t`) and related
APIs (`hcd_port_set_fifo_bias()`) have been removed in favor of the new structure-based mechanism.
The HCD initialization and port reset flow has been updated to use the explicit
FIFO configuration.
USB Host maintainer documentation (`maintainers.md`) has been updated accordingly.
Test cases were updated to remove the usage of removed bias API and now rely on default
or custom FIFO configuration.
