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c5ae121bacecaa1a0da6724f326ce2bc6e64349d
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5 Commits

Author SHA1 Message Date
Armando
ec27891af6 change(cache): swap cache hal arg 'type' and 'level' 2023-09-22 14:19:41 +08:00
Armando
cc581c3c36 change(cp_dma): check cache line by cache level 2023-09-22 14:19:41 +08:00
morris
6bb05cccdd feat(rmt): add driver support for esp32p4 
including DMA feature
 2023-09-19 12:54:14 +08:00
morris
595c3fe6a2 fix(async_memcpy): destination alignment check against cache line size 
On ESP32P4, becasue we need to invalidate the destination buffer,
if the buffer is not aligned to cache line, then it might break
other date structure, randomly.
 2023-08-15 17:40:17 +08:00
morris
fd3d1aa101 feat(async_memcpy): refactor driver code to support different DMA backen 
To support AHB and AXI DMA memory copy for the same target (esp32p4).
 2023-08-03 12:02:09 +08:00