7 Commits

Author	SHA1	Message	Date
Omar Chebib	5bcd9b2db8	G0: RISC-V targets have now an independent G0 layer ... G0 doesn't depend on any G1+ layer for RISC-V based targets	2022-06-14 15:00:53 +08:00
morris	83d16aa00c	gdma: support IRAM interrupt	2021-11-08 16:14:51 +08:00
morris	6e981af406	gdma: separate tx/rx channel interrupt	2021-05-06 15:06:37 +08:00
Marius Vikhammer	504a1e6102	soc: merge C3 caps into a single soc_caps.h	2021-04-28 14:42:35 +08:00
morris	e6d23a35ec	gdma: dynamic alloc DMA channels	2021-01-13 10:52:27 +08:00
Marius Vikhammer	1b6891c5d8	mbedtls: merge changes from C3	2020-12-29 10:56:13 +08:00
Angus Gratton	7c08be5771	hal: Add initial ESP32-C3 support ... From internal commit 7761d6e8	2020-11-30 15:23:15 +11:00