wuzhenghui
c84757d35e
fix(esp_hw_support): fix current leakage if ext32k slow clock source not exists
2025-04-08 20:07:47 +08:00
Chen Jichang
2cbc297969
refactor(gptimer): use group_id in clock ctrl functions
2025-04-08 10:20:48 +08:00
Laukik Hase
26fa7109f3
fix(esp_tee): Protect the AES/SHA clock registers from REE access
2025-02-25 16:49:08 +05:30
Armando
784e87a9b2
feat(ocode): supported ocode on esp32c5
2025-01-02 10:12:47 +08:00
Song Ruo Jing
7b852faf66
fix(esp_system): hp periph clk should not be gated on core/system reset
2024-11-29 21:42:06 +08:00
wuzhenghui
c067e406ce
fix(esp_system): deselect all modem modules clk source selection before clk init
2024-11-15 11:00:16 +08:00
wuzhenghui
7fdfa6c227
fix(esp_hw_support): disable unused clock sources after rtc clock switching complete
2024-10-28 15:57:26 +08:00
Song Ruo Jing
6afbc06666
feat(gdma): add retention support for esp32p4, esp32c5, esp32c61
2024-09-24 12:33:41 +08:00
wuzhenghui
05e74480f5
feat(esp_system): gate some clock by default to optmize esp32p4 active power
2024-09-11 10:53:00 +08:00
Xiao Xufeng
5b71b949be
fix(startup): move rtc initialization before MSPI timing tuning to improve stability
2024-06-18 01:16:24 +08:00
wuzhenghui
e7046e2abf
fix(esp_hw_support): fix bad logic in esp_perip_clk_init
2024-04-12 14:08:07 +08:00
wuzhenghui
4a64d2fe2c
change(hal): control PAU bus clock by hal layer
2024-03-29 00:36:46 +08:00
Marius Vikhammer
42fc463c81
fix(console): fixed CONSOLE_NONE not working on C2/C3
2024-03-26 13:39:10 +08:00
Darian Leung
a77e5cc718
refactor(hal/usb): Remove usb_fsls_phy_ll.h
...
For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.
This commit does the following:
- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.
2024-03-18 19:23:43 +08:00
Wu Zheng Hui
5a682c3bbb
Merge branch 'feature/optimize_chips_active_power' into 'master'
...
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state
Closes IDF-5658
See merge request espressif/esp-idf!27798
2024-03-14 12:08:33 +08:00
Konstantin Kondrashov
3f89072af1
feat(all): Use PRIx macro in all logs
2024-03-12 11:15:53 +02:00
wuzhenghui
9e8e20227f
feat(system): disable RNG module clock by default for save power
2024-03-12 10:10:41 +08:00
wuzhenghui
2a251982fc
feat(system): add option to allow user disable assist_debug module to save power
2024-03-12 10:10:40 +08:00
wuzhenghui
b0fa4565a1
feat(system): add option to allow user disable USJ module to save power
2024-03-12 10:10:36 +08:00
wuzhenghui
85b246ac88
feat(system): gate the debug clock source by default for esp32c6 and esp32h2
2024-03-07 19:26:39 +08:00
wuzhenghui
f5707c6ab8
feat(system): gate the REF_TICK clock by default for esp32c6 and esp32h2
2024-03-07 19:26:38 +08:00
wuzhenghui
60e985e7af
feat(system): gate the LP peripheral clock by default for esp32c6 and esp32h2
2024-03-07 19:26:38 +08:00
wuzhenghui
0528c8b4f4
feat(system): gate the HP peripheral clock by default for esp32c6 and esp32h2
2024-03-07 19:26:37 +08:00
liuning
3fa9c578f9
fix(clk): clear all lpclk source at clk init
2024-02-07 13:49:18 +08:00
Marius Vikhammer
06850e0e1e
refactor(system): removed esp_system from astyle ignore list and reformated it
2024-01-30 15:17:15 +08:00
Song Ruo Jing
cf93777077
refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
...
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
2024-01-25 19:15:33 +08:00
Cao Sen Miao
6768805d20
fix(uart,usj...): Fix wrong serial number that has been parsed to rom functions,
...
Closes https://github.com/espressif/esp-idf/issues/12958
2024-01-18 10:51:51 +08:00
wuzhenghui
6661e11203
fix(esp_hw_support): re-initialize icg map in modem_clock_module_enable
2023-11-17 14:05:23 +08:00
morris
71cf16ec01
feat(gptimer): use RCC atomic block to enable/reset peripheral
2023-08-22 17:05:35 +08:00
laokaiyao
ffb40a89d9
adc_cali: supported channel compensation of adc calibration on esp32c6
2023-05-23 22:44:25 +08:00
Gustavo Henrique Nihei
3cbac3dd1d
esp_system: Ensure TIMG0 clock is always enabled during normal operation
...
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com >
2023-03-06 04:58:11 +00:00
jingli
9c37441b17
wdt: refactor wdt codes to use unified type
2023-02-15 12:08:55 +08:00
Li Shuai
59cf87fe7d
pmu: sleep initialization and sleep start support for esp32c6
...
Initialize the pmu sleep machine constant when pmu is initialized, and calculate
the pmu sleep time adjustment value and hardware configuration value according
to the machine constant during system sleep.
Calibrate fast OSC before each sleep and use the calibration value to calculate
PMU hardware wait cycles when use the fast OSC as the work clock.
2023-01-31 22:12:27 +08:00
wuzhenghui
a5fdc53bb7
clk: initialize wifi lp_clk in esp_perip_clk_init
2022-12-29 13:13:37 +08:00
Li Shuai
e9172ddcea
initialize the clock gating control signal of each modem clock domain
2022-12-27 21:31:59 +08:00
Song Ruo Jing
182e937c5a
clk_tree: Add basic clock support for esp32c6
...
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
2022-12-13 19:18:34 +08:00
wuzhenghui
ab09c07fdd
esp32c6: add esp_system support
2022-09-06 09:13:20 +00:00
