Michael (XIAO Xufeng)
9468bc3784
Merge branch 'fix/check_ring_buffer_before_fill' into 'master'
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fix(uart): remove unnecessary wait when sending message to ring buffer
See merge request espressif/esp-idf!30839
2024-06-04 10:47:00 +08:00
Song Ruo Jing
dca7c286d0
feat(uart): support uart module sleep retention on c6/h2/p4
2024-06-03 12:40:43 +08:00
Xu Si Yu
95035c53df
fix(uart): remove unnecessary wait when sending message to ring buffer
2024-05-28 14:37:11 +08:00
Song Ruo Jing
8c603c24cd
fix(uart): re-initialize uart_event fields to some certain values for every loop
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Although uart_event.size and uart_event.timeout_flags fields are
meaningless to events other than UART_DATA, fix the values to 0 could
help reduce confusion.
Closes https://github.com/espressif/esp-idf/issues/12299
2024-04-24 19:19:04 +08:00
LiPeng
235bb6f294
fix(uart): Fixed issue that TX be blocked by auto-lightsleep
2024-04-05 03:01:24 +08:00
morris
c0289ee6eb
fix(drivers): fix typos found by codespell
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codespell components/esp_driver*
2024-03-28 10:01:27 +08:00
Song Ruo Jing
90bf2772ac
fix(uart): Fix mismatch wakeup rising edges required with the threshold configured
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Closes https://github.com/espressif/esp-idf/issues/12586
2024-03-15 16:58:33 +08:00
gaoxu
f9109beda2
feat(uart): add HP/LP uart support on ESP32C5
2024-02-29 14:12:51 +08:00
Song Ruo Jing
5276cd4f1d
refactor(uart): add support to be able to test LP_UART port
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Increase LP_UART_EMPTY_THRESH_DEFAULT value to 4. The original value
could cause the FIFO become empty before filling next data into the FIFO
when the buadrate is high. TX_DONE interrupt would raise before actual
transmission complete in such case.
2024-02-07 14:37:48 +08:00
laokaiyao
96a4ead083
feat(esp32c5): support to run hello world on esp32c5 beta3
2024-01-09 13:11:11 +08:00
Song Ruo Jing
ef281dff5a
fix(esp_driver_uart): always use heap_caps_malloc to malloc memory base on flags
2023-12-15 17:03:58 +08:00
Song Ruo Jing
6ad80f0332
refactor(uart): make uart driver as component, and fix astyle
2023-12-15 17:03:51 +08:00
