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541 Commits

Author SHA1 Message Date
Darian Leung
54eb152a96 TWAI: Simply caps and remove unused caps 2021-04-16 18:36:18 +08:00
Angus Gratton
268b23db96 bootloader: Fix selection of Quad I/O modes on ESP32-U4WDH chip 
Closes https://github.com/espressif/esp-idf/issues/6191
 2021-04-12 18:49:17 +10:00
morris
75dfd970b4 dac: added DAC support macro 
Remove DAC support on ESP32-S3
 2021-04-12 12:04:46 +08:00
Armando
9b9ea71ff9 spi: remove HSPI macro on esp32c3 and esp32s3 2021-04-06 13:42:49 +08:00
Michael (XIAO Xufeng)
3a90d51831 Merge branch 'refactor/using_isr_callback_in_timer_example' into 'master' 
TIMG: clean up timer example and add example test

Closes IDF-2722, IDF-2766, and IDF-2347

See merge request espressif/esp-idf!12218
 2021-03-22 06:36:32 +00:00
morris
f5ca47c0fc mcpwm: rename macros related to soc capbility 2021-03-16 21:53:59 +08:00
morris
5a520cacf1 timer_group: correct timer_ll_set_divider 2021-03-16 17:56:37 +08:00
Angus Gratton
fd164b82b6 Merge branch 'refactor/move_from_xtensa' into 'master' 
Movements from xtensa

Closes IDF-2164

See merge request espressif/esp-idf!10556
 2021-03-11 00:24:25 +00:00
Renz Bagaporo
1efdcd69d9 xtensa: move out trax 2021-02-26 19:45:48 +08:00
Xia Xiaotian
f53c0c5b87 esp_wifi: store PHY digital registers before disabling PHY and load 
them after enabling PHY
 2021-02-26 11:29:50 +08:00
morris
7b37158ede rmt: distinguish group and channel in HAL layer 2021-02-25 12:42:23 +08:00
morris
6dc7f95342 mcpwm: fix wrong meta information 2021-02-22 20:23:35 +08:00
Angus Gratton
2ec04b57de soc esp32: Removes parentheses from RTC_MEM_xyz macros that expand directly to single numbers 
Not necessary in these cases, and prevents parens from expanding into the
assembly code such as added in 562ab01046  -
a pattern which is accepted by GCC assembler but illegal syntax for LLVM assembler.

As reported https://github.com/espressif/llvm-project/issues/35#issuecomment-726853574
 2021-02-08 10:08:01 +11:00
Michael (XIAO Xufeng)
d7d1dee208 system: reset dma when soft reset 2021-01-25 04:51:40 +00:00
Angus Gratton
fe8a891de9 Merge branch 'feature/support_esp32c3_master_cmake_secure_boot' into 'master' 
bootloader/esp32c3: Support secure boot

Closes IDF-2115

See merge request espressif/esp-idf!11797
 2021-01-21 08:42:49 +08:00
KonstantinKondrashov
88c5fe49b8 soc: Adds a soc_caps define for all chips to define the number of boot key digests 2021-01-19 20:51:13 +08:00
Li Shuai
aa7fd175b9 light sleep: light sleep support for esp32c3 2021-01-19 14:50:58 +08:00
ninh
27aa6c289f components/pm: Add slp gpio configure workaround 2021-01-15 15:34:45 +08:00
morris
e6d23a35ec gdma: dynamic alloc DMA channels 2021-01-13 10:52:27 +08:00
ninh
dc7bdb9857 adjust lightsleep overhead time and cali slowclk 2021-01-06 03:40:28 +00:00
Marius Vikhammer
eb788deb03 esp_hw_support: merge C3 changes to master 
Merge RTC related C3 changes to master
 2020-12-30 12:20:41 +08:00
Angus Gratton
c3ba995f2c Merge branch 'ci/ccomp_performance_tests' into 'master' 
unit_test: Refactor all performance tests that rely on cache compensated timer

See merge request espressif/esp-idf!11709
 2020-12-24 13:44:52 +08:00
Angus Gratton
fa892eb017 soc: Explain units for rtc_clk_cal() function, fix typo 2020-12-23 09:53:24 +11:00
Cao Sen Miao
e338a2e3df rtc: add function to en/disable the rtc clock 2020-12-23 09:53:24 +11:00
Marius Vikhammer
0a95151a75 unit_test: Refactor all performance tests that rely on cache compensated timer 
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.

This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
 2020-12-22 18:56:24 +11:00
Cao Sen Miao
0736c91d68 soc: Remove cache constants from soc.h 2020-12-17 15:34:13 +11:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer 
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
 2020-12-10 09:04:47 +00:00
Angus Gratton
c29d93986d soc: Add initial ESP32-C3 support 
From internal commit 7761d6e8
 2020-11-30 11:12:56 +11:00
Armando
fb8b905539 uart: add uart support on esp32s3 2020-11-24 19:12:51 +08:00
morris
c5fe158929 doc: fix wrong register description regarding to ethernet SMI 2020-11-16 13:30:49 +08:00
Michael (XIAO Xufeng)
14944b181e Merge branch 'fix/soc_caps_spi_dummy_output_esp32' into 'master' 
soc_caps.h: remove spi cap that is defined to 0

See merge request espressif/esp-idf!11203
 2020-11-16 10:39:27 +08:00
Michael (XIAO Xufeng)
099fca515d Merge branch 'bugfix/move_crypto_caps' into 'master' 
SHA/RSA: moved all caps to soc_caps.h

Closes IDF-2300

See merge request espressif/esp-idf!11032
 2020-11-13 11:06:44 +08:00
Angus Gratton
935e4b4d62 Merge branch 'feature/riscv_arch' into 'master' 
Add RISC-V support

Closes IDF-2359

See merge request espressif/esp-idf!11140
 2020-11-13 07:50:31 +08:00
Angus Gratton
420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00
Cao Sen Miao
6eee601cf6 i2c: Add supports on esp32s3 2020-11-12 11:32:45 +08:00
Michael (XIAO Xufeng)
5b6c965e99 soc_caps.h: remove spi cap that is defined to 0 
According to the caps rule, for unsupported feature we don't define anything. 

Remove the define 0 that violates this rule.
 2020-11-12 10:29:42 +08:00
Marius Vikhammer
488f46acf5 SHA/RSA: moved all caps to soc_caps.h 2020-11-12 02:15:46 +00:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit) 
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
 2020-11-11 07:36:35 +00:00
morris
ff976867b3 rmt: split TX and RX in LL driver 
Split TX and RX function in LL driver.
Channel number is encoded in driver layer.
Added channel signal list in periph.c
 2020-11-05 19:00:55 +08:00
chenjianqiang
9465af0066 rmt: support esp32s3 2020-11-05 19:00:55 +08:00
morris
e4c8ec6174 timergroup: move interrupt index into peripheral description file 
1. Added timer_group_periph.c file, describing module global signals
   (e.g. interrupt index)
2. Added more caps in soc_caps.h
 2020-11-03 18:16:50 +08:00
Michael (XIAO Xufeng)
35faecea1d Merge branch 'feature/support_sigma_delta_on_s3' into 'master' 
sigma_delta: add periph signal list and support esp32-s3

See merge request espressif/esp-idf!10945
 2020-10-30 17:22:02 +08:00
Michael (XIAO Xufeng)
3bacf35310 esp_flash: support high capacity flash chips (32-bit address) 2020-10-29 18:20:11 +08:00
morris
17808b3ff8 sigma_delta: add periph signal list and support esp32-s3 2020-10-29 11:06:28 +08:00
Renz Bagaporo
79887fdc6c soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
Renz Christian Bagaporo
1f2e2fe8af soc: separate abstraction, description and implementation 2020-02-11 14:30:42 +05:00
Wangjialin
aaf119e930 flash(esp32s2): fix setting address field in spi user mode. 2020-02-07 16:10:51 +01:00
Ivan Grokhotkov
70752baba4 esp32s2: add brownout detector support 
1. add brownout detector HAL for esp32 and esp32s2
2. enable brownout reset for esp32 rev. 1 and above
3. add approximate brownout detector levels for esp32s2
 2020-01-23 13:44:19 +01:00
Angus Gratton
c7738f24fc Merge branch 'bugfix/ledc_driver_enums' into 'master' 
driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum

See merge request espressif/esp-idf!7021
 2020-01-10 15:34:43 +08:00
Darian Leung
a049e02d96 can: Refactor CAN to use HAL and LowLevel layers 
The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:

- Added bit field members to can_message_t as alternative
  to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
 2020-01-09 16:13:51 +08:00