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182 Commits

Author SHA1 Message Date
Song Ruo Jing
aa35807198 fix(clk): add an inevitable kconfig option to be selected to use rc32k 2024-11-26 21:20:32 +08:00
Song Ruo Jing
2cb35a2955 refactor(regi2c): ana i2c master clock is enabled per request 2024-11-04 12:37:17 +08:00
Song Ruo Jing
92ed77933b refactor(clk): deprecate SOC_RTC_FAST_CLK_SRC_XTAL_DIV 2024-11-04 12:37:17 +08:00
Hong Shu Qing
63fdde6cd4 Merge branch 'bugfix/chip823_pll_low_temp_bug' into 'master' 
[H2]Fix cpu switch fail for bbpll cali fail bug in low temp

See merge request espressif/esp-idf!31374
 2024-11-01 16:45:57 +08:00
wuzhenghui
3881d4031d fix(esp_hw_support): enable all supported slow clock at pmu_init 2024-10-24 14:22:51 +08:00
Hong Shu Qing
bae513ecaf Merge branch 'bugfix/fix_h2_wrong_lslp_drvb_config_bug' into 'master' 
fix(h2): fix lslp drvb config bug

See merge request espressif/esp-idf!30339
 2024-10-18 16:33:39 +08:00
Song Ruo Jing
7c0b1dc98c fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL 
Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips
For PMU supported chips, powering down CPU PLL in sleep will be done by PMU, not sleep code
 2024-10-17 12:41:15 +08:00
Song Ruo Jing
67a87a5fcd fix(pmu): enable all func clock icg during retention 
This should only increase a tiny amount of the power consumption in the retention process,
but save debug time since some module register read/write relies not only APB but also func clock.
 2024-10-17 12:41:15 +08:00
wuzhenghui
13e42707a0 feat(esp_hw_support): add clk tree source gate management api 2024-09-11 10:53:01 +08:00
wuzhenghui
05e74480f5 feat(esp_system): gate some clock by default to optmize esp32p4 active power 2024-09-11 10:53:00 +08:00
Li Shuai
1fa27cbb0d Merge branch 'feature/esp32c5mp_light_sleep_support_stage_2' into 'master' 
feat(esp_hw_support): esp32c5mp sleep support (system part)

Closes IDF-8643, PM-195, PM-169, IDF-8641, IDF-8640, IDF-8639, IDF-8638, CV-259, IDF-10308, IDF-10317, IDF-10310, PM-202, IDF-10918, PM-207, PM-208, PM-210, and PM-214

See merge request espressif/esp-idf!31645
 2024-08-29 19:32:05 +08:00
harshal.patil
95f286555a fix(esp_hw_support): Use _iram_text_end instead of _iram_end for I/D-RAM split 2024-08-28 11:16:27 +05:30
Lou Tianhao
d6737c3207 refactor(esp_hw_support): refactor sleep clock, split it to support multiple targets 2024-08-28 10:44:08 +08:00
Lou Tianhao
5e5fb89c10 change(esp_hw_support): modify the root clock source of pmu modem state to pll for esp32c5 2024-08-28 10:44:08 +08:00
Lou Tianhao
a0da9ade35 feat(esp_hw_support): support top domain powered down during sleep for esp32c5 2024-08-28 10:44:08 +08:00
laokaiyao
1c2f8b8ce0 feat(bootloader): support to check efuse block revision 
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
 2024-08-26 10:02:31 +08:00
harshal.patil
488b2a741d change(esp_security): Move the crypto locking layer into the security component 2024-08-20 12:35:22 +08:00
Song Ruo Jing
335d39b869 feat(clk): Add basic clock support for esp32c61 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-07-31 22:41:22 +08:00
Song Ruo Jing
3aa27ae960 refactor(regi2c): add LL function to control analog i2c master clock 2024-07-24 12:26:59 +08:00
hongshuqing
f3087c8fb0 fix: fix pll low temp bug 2024-07-08 14:40:51 +08:00
Song Ruo Jing
40f3bc2e57 feat(clk): Add basic clock support for esp32c5 mp 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-06-26 14:26:34 +08:00
Wu Zheng Hui
2d36e81ccd Merge branch 'fix/remove_esp32c6_h2_solved_todos' into 'master' 
change(esp_hw_support): remove esp32c6 & esp32h2 solved todos

Closes IDF-5781 and IDF-6254

See merge request espressif/esp-idf!31401
 2024-06-24 13:35:04 +08:00
wuzhenghui
1679b509be feat(esp_hw_support): support DCDC always on 2024-06-21 16:55:49 +08:00
Xiao Xufeng
5b71b949be fix(startup): move rtc initialization before MSPI timing tuning to improve stability 2024-06-18 01:16:24 +08:00
Song Ruo Jing
ac6101bf4e feat(clk): support ESP32C5 XTAL 40M/48M selection 2024-06-11 17:42:43 +08:00
wuzhenghui
083ef29dcd change(esp_hw_support): remove esp32c6 & esp32h2 solved todos 2024-06-11 10:20:23 +08:00
wuzhenghui
cca222948a fix(esp_driver_gpio): manage lp_io module clock by driver 
Closes https://github.com/espressif/esp-idf/issues/13683
 2024-06-05 17:56:37 +08:00
Michael (XIAO Xufeng)
438971c108 Merge branch 'feat/kconfig_h2_v1.0_dev' into 'master' 
esp32h2: add development support option for v1.0 chips

See merge request espressif/esp-idf!30534
 2024-05-21 17:20:56 +08:00
Hong Shu Qing
1a6060fa3a Merge branch 'feature/esp32c6_pu8m_in_sleep_support' into 'master' 
feat(sleep): support 8m force pu in sleep for esp32c6 & esp32h2

See merge request espressif/esp-idf!30532
 2024-05-17 11:34:47 +08:00
chaijie@espressif.com
36bbb64992 feat(sleep): support 8m force pu in sleep for esp32c6/esp32h2 2024-05-16 21:15:05 +08:00
Michael (XIAO Xufeng)
7bff9f9d28 feat(esp32h2): add development support option for v1.0 chips 2024-05-16 02:23:52 +08:00
Linda
52cfd1bf24 docs: fix clock sources for esp32c6 2024-05-07 17:35:39 +08:00
hongshuqing
2159ec7539 fix(h2): modify wrong lslp drvb config 2024-04-18 14:52:08 +08:00
Jiang Jiang Jian
9081d54aa7 Merge branch 'fix/fix_pmu_power_domain_initialize_order' into 'master' 
fix(esp_hw_support): fix pmu power domain initialize order

See merge request espressif/esp-idf!30095
 2024-04-10 17:23:47 +08:00
morris
e8b6d2280d change(gptimer): use private unsafe RCC LL functions in bootloader 2024-04-08 17:48:20 +08:00
wuzhenghui
24244f04f2 fix(esp_hw_support): fix pmu power domain initialize order 2024-04-08 15:47:59 +08:00
Laukik Hase
48503dd39f fix(esp_hw_support): Fix the flash I/DROM region PMP protection 2024-04-02 18:41:07 +05:30
Li Shuai
262be04b21 change(esp_hw_support): modify system and modem clock to support modem domain power down 2024-03-29 16:13:52 +08:00
wuzhenghui
194c38479e refactor(esp_hw_support): split pd_top clock retention initialization by target 2024-03-28 19:18:24 +08:00
Omar Chebib
a79c6f7f67 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-03-27 16:21:25 +08:00
Wu Zheng Hui
5a682c3bbb Merge branch 'feature/optimize_chips_active_power' into 'master' 
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
 2024-03-14 12:08:33 +08:00
Jiang Jiang Jian
6a879bf2d2 Merge branch 'bugfix/fix_maximum_value_of_config_rtc_clk_cal_cycles_bug' into 'master' 
ESP All Chip: fixed the maximum value of config RTC_CLK_CAL_SYCLES bug

See merge request espressif/esp-idf!29423
 2024-03-14 10:44:17 +08:00
wuzhenghui
129bfce02e feat(esp_hw_support): support esp32p4 pll start/stop event callback 2024-03-10 10:51:28 +08:00
wuzhenghui
856f043331 feat(esp_hw_support): add esp32p4 pmu initial support 2024-03-10 10:51:28 +08:00
wuzhenghui
f5707c6ab8 feat(system): gate the REF_TICK clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
Omar Chebib
eeb5e2f080 Merge branch 'refactor/cpu_interrupt_table' into 'master' 
refactor(Core System/Interrupts): changed reserved interrupt functions to be now defined per SoC

Closes IDF-5728

See merge request espressif/esp-idf!29020
 2024-03-06 11:26:17 +08:00
hongshuqing
d78805670a fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug 2024-03-05 19:33:30 +08:00
Omar Chebib
c1849df791 refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC 2024-02-28 15:21:10 +08:00
Laukik Hase
366e4ee944 refactor(esp_hw_support): Remove redundant PMP entry for ROM region 
- The ROM text and data sections share the address range
    (see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
  - Initially, we had two PMP entries for this address range - one marking the
    region as RX and the other as R.
  - However, the latter entry is redundant as the former locks the PMP settings.
  - We can divide the ROM region into text and data sections later when we
    define boundaries marking these regions from the ROM.
 2024-02-28 10:54:38 +05:30
Laukik Hase
ff839be31d fix(esp_hw_support): Fix the I/DCACHE region PMP protection 2024-02-28 10:54:37 +05:30