Harshal Patil
b873a82d5b
Merge branch 'feat/generic_key_mgr_key_types' into 'master'
...
Store key_len field in the key_config
See merge request espressif/esp-idf!42692
2025-11-18 15:12:03 +05:30
harshal.patil
1c1bcf44be
feat(esp_security): Support ECDSA-P384 key deployment using Key Manager
2025-11-17 12:34:09 +05:30
harshal.patil
1f2cbde525
change(esp_key_mgr): Store key_len field in the key_info
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- Update the Key Manager key types to be generic
- Define a new enum to determine the length of the keys
- Refactor the Key Manager driver support generic key types and key lengths
- Also store key deployment mode in the key recovery info
2025-11-17 12:34:09 +05:30
C.S.M
a90c93541c
feat(esp32s31): Introduce new target esp32s31
2025-11-17 14:48:55 +08:00
Mahavir Jain
4a53c4e651
Merge branch 'bugfix/esp32c5_encrypted_flash_write_v2' into 'master'
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fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
See merge request espressif/esp-idf!43301
2025-11-13 18:01:04 +05:30
Harshal Patil
0debe71b3d
Merge branch 'feat/flash_enc_using_key_manager' into 'master'
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Support Flash Encryption using Key Manager
Closes IDF-13462 and IDF-14278
See merge request espressif/esp-idf!41879
2025-11-13 07:55:15 +05:30
Mahavir Jain
3c5d2e6b58
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.
This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
2025-11-12 19:14:55 +05:30
harshal.patil
540c719c66
change(esp_key_mgr): Make Key Manager driver bootloader compatible
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- Independent of heap
2025-11-11 12:23:26 +05:30
harshal.patil
8abea3c537
feat(bootloader_support): Support Flash Encryption using Key Manager
2025-11-11 12:23:25 +05:30
harshal.patil
304bd1c77b
fix(esp_security/esp_key_mgr): Fix missed error codes and some cleanup
2025-11-11 12:22:08 +05:30
harshal.patil
3090e91e60
fix(esp_security): Set WR_DIS_SECURE_BOOT_SHA384_EN by default when
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Flash Encryption Release mode is enabled and Secure Boot P384 scheme not is enabled.
2025-11-05 08:39:55 +05:30
harshal.patil
7168b9f7d3
fix(esp_security): Fix undefined efuse build failure in case of ESP32-P4
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- The `wr_dis` efuse bit corresponding to `SECURE_BOOT_SHA384_EN` is absent in P4
2025-11-05 08:39:55 +05:30
harshal.patil
609d52c6bf
feat(esp32p4): Support newer Key Manager key sources for ESP32-P4 V3
2025-10-15 15:49:20 +05:30
Harshal Patil
fd7d9c9ee9
Merge branch 'fix/key_mgr_use_default_efuse_key' into 'master'
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Configure the Key Manager to use XTS-AES efuse key by-default
Closes IDFCI-3135 and IDFCI-3136
See merge request espressif/esp-idf!42032
2025-09-26 12:34:19 +05:30
harshal.patil
8b663ebe4d
fix(esp_security): Configure the Key Manager to use XTS-AES efuse key by-default
2025-09-22 12:22:07 +05:30
harshal.patil
5aa5366e7f
fix(bootloader_support): Reorder write disabling ECDSA_CURVE_MODE
2025-09-19 17:01:23 +05:30
harshal.patil
d6c1184676
fix(bootloader_support): Reorder write protection bits of some shared security efuses
2025-09-19 13:02:00 +05:30
harshal.patil
854ec3590f
fix(esp_key_mgr): Fix incorrect key manager state management
2025-09-12 11:02:45 +05:30
harshal.patil
9e87b50307
change(mbedtls/ecdsa): The ECDSA module of ESP32-H2 ECO5 does not use MPI module
2025-08-11 12:08:51 +05:30
harshal.patil
dce0925f40
fix(esp_security/esp_key_mgr): Incorrect overlapping comparisons
2025-07-03 15:05:50 +05:30
harshal.patil
bba1448128
feat(esp_key_mgr): Support PSRAM XTS-AES key deployments using Key Manager
2025-06-27 15:15:26 +05:30
harshal.patil
50c41c3b59
change(esp_key_mgr): Refactor Key Manager driver to reduce logs
2025-06-27 15:15:26 +05:30
harshal.patil
a7af364112
fix(esp_security): Power up MPI memory registers when enabling MPI
...
Co-authored-by: Li HongXi <lihongxi@espressif.com >
2025-06-27 15:15:26 +05:30
harshal.patil
33d8c05d95
feat(esp_key_mgr): Support Digital Signature key deployments using Key Manager
2025-06-27 15:15:26 +05:30
harshal.patil
265b0d7579
feat(esp_key_mgr): Support HMAC key deployments using Key Manager
2025-06-27 15:15:26 +05:30
harshal.patil
8ab6b4d694
fix(esp_security/esp_key_mgr): Recharge HUK before the first usage
2025-06-27 15:15:26 +05:30
harshal.patil
a7c7b75dfd
feat(soc): Update ESP32-C5's key manager reg and struct files to ECO2
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- Also added a new soc_cap to denote if key manager key deployment is available
2025-06-27 15:15:26 +05:30
Aditya Patwardhan
662d793f37
feat(esp_security): Added support for key manager for esp32c5
2025-06-27 15:15:26 +05:30
nilesh.kale
c65858287a
feat: enabled secure boot support esp32h21
2025-04-25 17:48:25 +05:30
Laukik Hase
fc4802c0d6
feat(esp_tee): Protect the HMAC and DS peripherals from REE access
2025-04-16 19:19:04 +05:30
Laukik Hase
1c4969bc47
feat(esp_security): Add a TEE-specific crypto lock layer with stub implementations
2025-04-16 19:19:03 +05:30
nilesh.kale
aae4bfb6f3
feat: enable ecdsa support for esp32h21
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This commit enabled suppot for ECDSA peripheral in ESP32H21.
2025-04-14 10:26:46 +05:30
Laukik Hase
3e95020c59
refactor(esp_security): Introduce dedicated APIs for crypto clock configuration
2025-04-04 10:31:27 +05:30
Mahavir Jain
ce7ec7f19f
Merge branch 'feature/enable_hmac_and_ds_support_for_esp32h21' into 'master'
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feat: enabled hmac and ds support in esp32h21
Closes IDF-11495 and IDF-11497
See merge request espressif/esp-idf!37085
2025-03-21 17:23:46 +08:00
Chen Jichang
45ba78940f
feat(esp32h4): finnal introduce hello world
2025-03-19 18:48:41 +08:00
nilesh.kale
f794eb9b2d
feat: enabled hmac and ds support in esp32h21
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This commit enables support for HMAC and DS in ESP32H21
2025-03-13 10:23:11 +05:30
Chen Jichang
6f83f39dce
feat(esp32h4): introduce target esp32h4(stage 1)
2025-02-08 17:07:44 +08:00
laokaiyao
9269b785f8
refactor(ecdsa): rely on efuse to get chip revision
2025-01-24 11:50:17 +08:00
Aditya Patwardhan
d8d9ba3dc2
fix(soc): Fixed ECDSA register compatibility
2025-01-24 11:50:17 +08:00
Aditya Patwardhan
bef2a72ecb
fix(hal): Make the ECDSA countermeasure dynamically applicable
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This commit makes the ECDSA countermeasure dynamically applicable
across different revisions of the ESP32H2 SoC.
2025-01-24 11:50:17 +08:00
Mahavir Jain
6875cbf022
feat(ecc): enable ECC constant time mode for ESP32-H2 ECO5
2025-01-24 11:50:17 +08:00
gaoxu
25731d0c1e
feat(esp32h21): finnal introduce hello world support
2024-12-30 20:14:40 +08:00
gaoxu
64bbb53b8f
feat(esp32h21): introduce target esp32h21(stage 1)
2024-11-12 15:42:27 +08:00
Aditya Patwardhan
82db0feab2
fix(security): Update key manager specific initializations for esp32c5
2024-10-28 11:13:43 +08:00
Mahavir Jain
e52e2d282a
refactor(startup): move key manager specific code to esp_security component
2024-09-25 14:21:19 +05:30
harshal.patil
e1cd5b909e
fix(esp_security): Fix build failure when dpa protection at startup is disabled
2024-09-20 18:46:55 +05:30
harshal.patil
39872a5575
feat(esp_security): Config to forcefully enable ECC constant-time operations during bootup
2024-09-20 18:46:55 +05:30
Mahavir Jain
a71e0fc028
Merge branch 'feature/enable_sha_support_for_esp32c61' into 'master'
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feat: enable support for sha peripheral in esp32c61
Closes IDF-9234
See merge request espressif/esp-idf!32830
2024-09-20 13:22:14 +08:00
nilesh.kale
12fc7a677e
feat: enable support for sha peripheral in esp32c61
2024-09-11 14:49:01 +05:30
harshal.patil
3b97011e39
fix(esp_security/ds): Clean up DS trying to re-acquire MPI lock post common crypto lock layer
2024-08-23 17:53:55 +05:30
