6 Commits

Author	SHA1	Message	Date
Ivan Grokhotkov	f355ecac40	ci(sdspi): re-enable probe/rw tests for slot 1 ... These tests were disabled since SDMMC_FREQ_HIGHSPEED with sdspi didn't work on ESP32 and ESP32-S3. However we don't have other tests for slot 1, meaning that we weren't running probe and perf tests at all. This commit re-enables the tests, keeping them with SDMMC_FREQ_DEFAULT	2024-05-02 16:44:16 +02:00
Ivan Grokhotkov	e672d49db7	fix(sdspi): fix memory leak in do_one_sdspi_probe test	2024-05-02 16:44:16 +02:00
Ivan Grokhotkov	6b6de47308	feat(sdspi): add LDO (power control) in sdspi tests	2024-04-04 15:03:27 +02:00
sonika.rathi	a7a0245d8e	fix(sdmmc): Migrate erase/trim test cases from unit-test-app to component-test-app	2023-12-06 11:07:33 +01:00
Armando	1400f3553d	change(sdspi): disabled some tests (needs check/re-enable future)	2023-11-29 12:13:03 +08:00
Armando	4aadacbcdc	refactor(sdspi): added component pytest cases and enabled them on CI	2023-11-29 12:13:03 +08:00