Chen Jichang
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2cbc297969
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refactor(gptimer): use group_id in clock ctrl functions
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2025-04-08 10:20:48 +08:00 |
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Song Ruo Jing
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c5ab71e3db
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fix(esp_system): still gate hp periph clk on core/system reset for power saving
Leaving only hp periph clk source should not be gated on core/system reset
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2024-12-12 20:45:06 +08:00 |
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Song Ruo Jing
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7b852faf66
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fix(esp_system): hp periph clk should not be gated on core/system reset
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2024-11-29 21:42:06 +08:00 |
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Song Ruo Jing
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aa35807198
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fix(clk): add an inevitable kconfig option to be selected to use rc32k
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2024-11-26 21:20:32 +08:00 |
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morris
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83c9cffd2b
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change(soc): vectorize bitscrambler regsiter layout
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2024-11-14 17:26:57 +08:00 |
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Jeroen Domburg
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ab75a94877
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feat(bitscrambler): add hal driver support
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2024-11-14 17:26:57 +08:00 |
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wuzhenghui
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7fdfa6c227
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fix(esp_hw_support): disable unused clock sources after rtc clock switching complete
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2024-10-28 15:57:26 +08:00 |
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wuzhenghui
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04b2afed44
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change(esp_hw_support): switch lp_cpu power mode with clock src to save lp_cpu working power
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2024-09-26 11:23:06 +08:00 |
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Marius Vikhammer
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564d777018
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Merge branch 'feature/lp_core_40_mhz' into 'master'
feat(system): support choosing xtal as rtc-fast clock src on P4 and C5
Closes IDF-10203
See merge request espressif/esp-idf!32450
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2024-09-20 10:57:15 +08:00 |
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Marius Vikhammer
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00eb97725b
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feat(system): support choosing xtal as rtc-fast clock src on P4 and C5
With xtal as rtc-fast clock source the LP-Core can run at twice the default
clock frequency. 40 MHz as opposed to 20 MHz.
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2024-09-19 17:30:44 +08:00 |
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wuzhenghui
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05e74480f5
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feat(esp_system): gate some clock by default to optmize esp32p4 active power
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2024-09-11 10:53:00 +08:00 |
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harshal.patil
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b729a0a732
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change(esp_security): Move crypto clk configuration into the security component
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2024-08-20 12:35:22 +08:00 |
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Armando
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5fe080ea5a
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fix(rtc): fixed non-iram rtc code in early stage on p4 leading xip_psram stuck
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2024-06-26 17:30:59 +08:00 |
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Xiao Xufeng
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5b71b949be
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fix(startup): move rtc initialization before MSPI timing tuning to improve stability
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2024-06-18 01:16:24 +08:00 |
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wuzhenghui
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f3d963a93b
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fix(esp_system): update power domain configuration with slow clock source selection
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2024-04-17 15:45:52 +08:00 |
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Marius Vikhammer
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42fc463c81
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fix(console): fixed CONSOLE_NONE not working on C2/C3
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2024-03-26 13:39:10 +08:00 |
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Konstantin Kondrashov
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3f89072af1
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feat(all): Use PRIx macro in all logs
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2024-03-12 11:15:53 +02:00 |
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nilesh.kale
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f6a7fb13cd
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feat: re enables tests on p4
This commit re-enables mbedtls and hal/crypto testapos on p4.
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2024-03-05 17:48:05 +08:00 |
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liuning
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3fa9c578f9
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fix(clk): clear all lpclk source at clk init
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2024-02-07 13:49:18 +08:00 |
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Marius Vikhammer
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06850e0e1e
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refactor(system): removed esp_system from astyle ignore list and reformated it
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2024-01-30 15:17:15 +08:00 |
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Song Ruo Jing
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cf93777077
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refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
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2024-01-25 19:15:33 +08:00 |
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Cao Sen Miao
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6768805d20
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fix(uart,usj...): Fix wrong serial number that has been parsed to rom functions,
Closes https://github.com/espressif/esp-idf/issues/12958
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2024-01-18 10:51:51 +08:00 |
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Song Ruo Jing
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7f2b85b82b
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feat(clk): add basic clock support for esp32p4
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
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2023-12-29 00:37:26 +08:00 |
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wuzhenghui
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6661e11203
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fix(esp_hw_support): re-initialize icg map in modem_clock_module_enable
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2023-11-17 14:05:23 +08:00 |
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Armando
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a336b94527
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feat(esp_system): base support on p4
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2023-07-25 05:59:10 +00:00 |
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